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Searched refs:ixAZALIA_INPUT_CRC1_CHANNEL2 (Results 1 – 17 of 17) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_10_0_d.h6710 #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 macro
Ddce_11_0_d.h6872 #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 macro
Ddce_11_2_d.h8217 #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 macro
Ddce_12_0_offset.h18098 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h7381 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
Ddcn_3_0_1_offset.h12224 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
Ddcn_2_1_0_offset.h12828 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
Ddcn_1_0_offset.h13068 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
Ddcn_3_1_4_offset.h194 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
Ddcn_3_2_1_offset.h13514 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
Ddcn_3_1_2_offset.h14038 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
Ddcn_3_2_0_offset.h13535 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
Ddcn_3_1_5_offset.h14144 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
Ddcn_3_0_2_offset.h15117 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
Ddcn_3_1_6_offset.h14635 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
Ddcn_2_0_0_offset.h16492 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro
Ddcn_3_0_0_offset.h16841 #define ixAZALIA_INPUT_CRC1_CHANNEL2 … macro