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Searched refs:ixAZALIA_INPUT_CRC0_CHANNEL5 (Results 1 – 17 of 17) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_10_0_d.h6700 #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 macro
Ddce_11_0_d.h6862 #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 macro
Ddce_11_2_d.h8207 #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 macro
Ddce_12_0_offset.h18089 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h7372 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
Ddcn_3_0_1_offset.h12215 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
Ddcn_2_1_0_offset.h12819 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
Ddcn_1_0_offset.h13059 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
Ddcn_3_1_4_offset.h185 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
Ddcn_3_2_1_offset.h13505 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
Ddcn_3_1_2_offset.h14029 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
Ddcn_3_2_0_offset.h13526 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
Ddcn_3_1_5_offset.h14135 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
Ddcn_3_0_2_offset.h15108 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
Ddcn_3_1_6_offset.h14626 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
Ddcn_2_0_0_offset.h16483 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro
Ddcn_3_0_0_offset.h16832 #define ixAZALIA_INPUT_CRC0_CHANNEL5 … macro