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Searched refs:ixAZALIA_INPUT_CRC0_CHANNEL2 (Results 1 – 17 of 17) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_10_0_d.h6697 #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 macro
Ddce_11_0_d.h6859 #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 macro
Ddce_11_2_d.h8204 #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 macro
Ddce_12_0_offset.h18086 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h7369 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
Ddcn_3_0_1_offset.h12212 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
Ddcn_2_1_0_offset.h12816 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
Ddcn_1_0_offset.h13056 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
Ddcn_3_1_4_offset.h182 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
Ddcn_3_2_1_offset.h13502 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
Ddcn_3_1_2_offset.h14026 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
Ddcn_3_2_0_offset.h13523 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
Ddcn_3_1_5_offset.h14132 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
Ddcn_3_0_2_offset.h15105 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
Ddcn_3_1_6_offset.h14623 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
Ddcn_2_0_0_offset.h16480 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro
Ddcn_3_0_0_offset.h16829 #define ixAZALIA_INPUT_CRC0_CHANNEL2 … macro