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Searched refs:ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE (Results 1 – 19 of 19) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h156 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 macro
Ddce_8_0_d.h5385 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 macro
Ddce_10_0_d.h6619 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 macro
Ddce_11_0_d.h6781 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 macro
Ddce_11_2_d.h8126 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 macro
Ddce_12_0_offset.h17971 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h7286 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
Ddcn_3_0_1_offset.h12129 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
Ddcn_2_1_0_offset.h12733 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
Ddcn_1_0_offset.h12973 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
Ddcn_3_1_4_offset.h1600 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
Ddcn_3_2_1_offset.h13419 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
Ddcn_3_1_2_offset.h13943 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
Ddcn_3_2_0_offset.h13440 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
Ddcn_3_1_5_offset.h14049 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
Ddcn_3_0_2_offset.h15022 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
Ddcn_3_1_6_offset.h14540 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
Ddcn_2_0_0_offset.h16397 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro
Ddcn_3_0_0_offset.h16746 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … macro