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Searched refs:ixAZALIA_CRC0_CHANNEL0 (Results 1 – 18 of 18) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h5450 #define ixAZALIA_CRC0_CHANNEL0 0x0 macro
Ddce_10_0_d.h6721 #define ixAZALIA_CRC0_CHANNEL0 0x0 macro
Ddce_11_0_d.h6883 #define ixAZALIA_CRC0_CHANNEL0 0x0 macro
Ddce_11_2_d.h8228 #define ixAZALIA_CRC0_CHANNEL0 0x0 macro
Ddce_12_0_offset.h18108 #define ixAZALIA_CRC0_CHANNEL0 … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h7391 #define ixAZALIA_CRC0_CHANNEL0 … macro
Ddcn_3_0_1_offset.h12234 #define ixAZALIA_CRC0_CHANNEL0 … macro
Ddcn_2_1_0_offset.h12838 #define ixAZALIA_CRC0_CHANNEL0 … macro
Ddcn_1_0_offset.h13078 #define ixAZALIA_CRC0_CHANNEL0 … macro
Ddcn_3_1_4_offset.h204 #define ixAZALIA_CRC0_CHANNEL0 … macro
Ddcn_3_2_1_offset.h13524 #define ixAZALIA_CRC0_CHANNEL0 … macro
Ddcn_3_1_2_offset.h14048 #define ixAZALIA_CRC0_CHANNEL0 … macro
Ddcn_3_2_0_offset.h13545 #define ixAZALIA_CRC0_CHANNEL0 … macro
Ddcn_3_1_5_offset.h14154 #define ixAZALIA_CRC0_CHANNEL0 … macro
Ddcn_3_0_2_offset.h15127 #define ixAZALIA_CRC0_CHANNEL0 … macro
Ddcn_3_1_6_offset.h14645 #define ixAZALIA_CRC0_CHANNEL0 … macro
Ddcn_2_0_0_offset.h16502 #define ixAZALIA_CRC0_CHANNEL0 … macro
Ddcn_3_0_0_offset.h16851 #define ixAZALIA_CRC0_CHANNEL0 … macro