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Searched refs:intr_vsync (Results 1 – 18 of 18) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_8_0_sc8280xp.h330 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
340 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
350 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
360 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
370 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
380 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
390 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
400 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
410 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
Ddpu_5_1_sc8180x.h316 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
326 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
336 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
348 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
358 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
368 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
Ddpu_3_0_msm8998.h246 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
255 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
264 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
272 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_4_0_sdm845.h262 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
271 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
280 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
289 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_7_2_sc7280.h196 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
206 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
216 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
Ddpu_5_0_sm8150.h309 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
319 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
329 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
339 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_6_0_sm8250.h308 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
318 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
328 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
338 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_7_0_sm8350.h332 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
342 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
352 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
362 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_8_1_sm8450.h354 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
364 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
374 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
384 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_9_0_sm8550.h353 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
363 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
373 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
383 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
Ddpu_5_4_sm6125.h153 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
163 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
Ddpu_6_2_sc7180.h144 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
154 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
Ddpu_6_4_sm6350.h160 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
170 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
Ddpu_6_5_qcm2290.h98 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
Ddpu_6_3_sm6115.h99 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
Ddpu_6_9_sm6375.h109 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
/linux-6.6.21/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_catalog.h609 s32 intr_vsync; member
Ddpu_encoder_phys_vid.c355 phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync; in dpu_encoder_phys_vid_atomic_mode_set()