1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_CONTEXT_TYPES__ 7 #define __INTEL_CONTEXT_TYPES__ 8 9 #include <linux/average.h> 10 #include <linux/kref.h> 11 #include <linux/list.h> 12 #include <linux/mutex.h> 13 #include <linux/types.h> 14 15 #include "i915_active_types.h" 16 #include "i915_sw_fence.h" 17 #include "i915_utils.h" 18 #include "intel_engine_types.h" 19 #include "intel_sseu.h" 20 21 #include "uc/intel_guc_fwif.h" 22 23 #define CONTEXT_REDZONE POISON_INUSE 24 DECLARE_EWMA(runtime, 3, 8); 25 26 struct i915_gem_context; 27 struct i915_gem_ww_ctx; 28 struct i915_vma; 29 struct intel_breadcrumbs; 30 struct intel_context; 31 struct intel_ring; 32 33 struct intel_context_ops { 34 unsigned long flags; 35 #define COPS_HAS_INFLIGHT_BIT 0 36 #define COPS_HAS_INFLIGHT BIT(COPS_HAS_INFLIGHT_BIT) 37 38 #define COPS_RUNTIME_CYCLES_BIT 1 39 #define COPS_RUNTIME_CYCLES BIT(COPS_RUNTIME_CYCLES_BIT) 40 41 int (*alloc)(struct intel_context *ce); 42 43 void (*revoke)(struct intel_context *ce, struct i915_request *rq, 44 unsigned int preempt_timeout_ms); 45 46 void (*close)(struct intel_context *ce); 47 48 int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr); 49 int (*pin)(struct intel_context *ce, void *vaddr); 50 void (*unpin)(struct intel_context *ce); 51 void (*post_unpin)(struct intel_context *ce); 52 53 void (*cancel_request)(struct intel_context *ce, 54 struct i915_request *rq); 55 56 void (*enter)(struct intel_context *ce); 57 void (*exit)(struct intel_context *ce); 58 59 void (*sched_disable)(struct intel_context *ce); 60 61 void (*update_stats)(struct intel_context *ce); 62 63 void (*reset)(struct intel_context *ce); 64 void (*destroy)(struct kref *kref); 65 66 /* virtual/parallel engine/context interface */ 67 struct intel_context *(*create_virtual)(struct intel_engine_cs **engine, 68 unsigned int count, 69 unsigned long flags); 70 struct intel_context *(*create_parallel)(struct intel_engine_cs **engines, 71 unsigned int num_siblings, 72 unsigned int width); 73 struct intel_engine_cs *(*get_sibling)(struct intel_engine_cs *engine, 74 unsigned int sibling); 75 }; 76 77 struct intel_context { 78 /* 79 * Note: Some fields may be accessed under RCU. 80 * 81 * Unless otherwise noted a field can safely be assumed to be protected 82 * by strong reference counting. 83 */ 84 union { 85 struct kref ref; /* no kref_get_unless_zero()! */ 86 struct rcu_head rcu; 87 }; 88 89 struct intel_engine_cs *engine; 90 struct intel_engine_cs *inflight; 91 #define __intel_context_inflight(engine) ptr_mask_bits(engine, 3) 92 #define __intel_context_inflight_count(engine) ptr_unmask_bits(engine, 3) 93 #define intel_context_inflight(ce) \ 94 __intel_context_inflight(READ_ONCE((ce)->inflight)) 95 #define intel_context_inflight_count(ce) \ 96 __intel_context_inflight_count(READ_ONCE((ce)->inflight)) 97 98 struct i915_address_space *vm; 99 struct i915_gem_context __rcu *gem_context; 100 101 /* 102 * @signal_lock protects the list of requests that need signaling, 103 * @signals. While there are any requests that need signaling, 104 * we add the context to the breadcrumbs worker, and remove it 105 * upon completion/cancellation of the last request. 106 */ 107 struct list_head signal_link; /* Accessed under RCU */ 108 struct list_head signals; /* Guarded by signal_lock */ 109 spinlock_t signal_lock; /* protects signals, the list of requests */ 110 111 struct i915_vma *state; 112 u32 ring_size; 113 struct intel_ring *ring; 114 struct intel_timeline *timeline; 115 116 unsigned long flags; 117 #define CONTEXT_BARRIER_BIT 0 118 #define CONTEXT_ALLOC_BIT 1 119 #define CONTEXT_INIT_BIT 2 120 #define CONTEXT_VALID_BIT 3 121 #define CONTEXT_CLOSED_BIT 4 122 #define CONTEXT_USE_SEMAPHORES 5 123 #define CONTEXT_BANNED 6 124 #define CONTEXT_FORCE_SINGLE_SUBMISSION 7 125 #define CONTEXT_NOPREEMPT 8 126 #define CONTEXT_LRCA_DIRTY 9 127 #define CONTEXT_GUC_INIT 10 128 #define CONTEXT_PERMA_PIN 11 129 #define CONTEXT_IS_PARKING 12 130 #define CONTEXT_EXITING 13 131 132 struct { 133 u64 timeout_us; 134 } watchdog; 135 136 u32 *lrc_reg_state; 137 union { 138 struct { 139 u32 lrca; 140 u32 ccid; 141 }; 142 u64 desc; 143 } lrc; 144 u32 tag; /* cookie passed to HW to track this context on submission */ 145 146 /** stats: Context GPU engine busyness tracking. */ 147 struct intel_context_stats { 148 u64 active; 149 150 /* Time on GPU as tracked by the hw. */ 151 struct { 152 struct ewma_runtime avg; 153 u64 total; 154 u32 last; 155 I915_SELFTEST_DECLARE(u32 num_underflow); 156 I915_SELFTEST_DECLARE(u32 max_underflow); 157 } runtime; 158 } stats; 159 160 unsigned int active_count; /* protected by timeline->mutex */ 161 162 atomic_t pin_count; 163 struct mutex pin_mutex; /* guards pinning and associated on-gpuing */ 164 165 /** 166 * active: Active tracker for the rq activity (inc. external) on this 167 * intel_context object. 168 */ 169 struct i915_active active; 170 171 const struct intel_context_ops *ops; 172 173 /** sseu: Control eu/slice partitioning */ 174 struct intel_sseu sseu; 175 176 /** 177 * pinned_contexts_link: List link for the engine's pinned contexts. 178 * This is only used if this is a perma-pinned kernel context and 179 * the list is assumed to only be manipulated during driver load 180 * or unload time so no mutex protection currently. 181 */ 182 struct list_head pinned_contexts_link; 183 184 u8 wa_bb_page; /* if set, page num reserved for context workarounds */ 185 186 struct { 187 /** @lock: protects everything in guc_state */ 188 spinlock_t lock; 189 /** 190 * @sched_state: scheduling state of this context using GuC 191 * submission 192 */ 193 u32 sched_state; 194 /* 195 * @fences: maintains a list of requests that are currently 196 * being fenced until a GuC operation completes 197 */ 198 struct list_head fences; 199 /** 200 * @blocked: fence used to signal when the blocking of a 201 * context's submissions is complete. 202 */ 203 struct i915_sw_fence blocked; 204 /** @requests: list of active requests on this context */ 205 struct list_head requests; 206 /** @prio: the context's current guc priority */ 207 u8 prio; 208 /** 209 * @prio_count: a counter of the number requests in flight in 210 * each priority bucket 211 */ 212 u32 prio_count[GUC_CLIENT_PRIORITY_NUM]; 213 /** 214 * @sched_disable_delay_work: worker to disable scheduling on this 215 * context 216 */ 217 struct delayed_work sched_disable_delay_work; 218 } guc_state; 219 220 struct { 221 /** 222 * @id: handle which is used to uniquely identify this context 223 * with the GuC, protected by guc->submission_state.lock 224 */ 225 u16 id; 226 /** 227 * @ref: the number of references to the guc_id, when 228 * transitioning in and out of zero protected by 229 * guc->submission_state.lock 230 */ 231 atomic_t ref; 232 /** 233 * @link: in guc->guc_id_list when the guc_id has no refs but is 234 * still valid, protected by guc->submission_state.lock 235 */ 236 struct list_head link; 237 } guc_id; 238 239 /** 240 * @destroyed_link: link in guc->submission_state.destroyed_contexts, in 241 * list when context is pending to be destroyed (deregistered with the 242 * GuC), protected by guc->submission_state.lock 243 */ 244 struct list_head destroyed_link; 245 246 /** @parallel: sub-structure for parallel submission members */ 247 struct { 248 union { 249 /** 250 * @child_list: parent's list of children 251 * contexts, no protection as immutable after context 252 * creation 253 */ 254 struct list_head child_list; 255 /** 256 * @child_link: child's link into parent's list of 257 * children 258 */ 259 struct list_head child_link; 260 }; 261 /** @parent: pointer to parent if child */ 262 struct intel_context *parent; 263 /** 264 * @last_rq: last request submitted on a parallel context, used 265 * to insert submit fences between requests in the parallel 266 * context 267 */ 268 struct i915_request *last_rq; 269 /** 270 * @fence_context: fence context composite fence when doing 271 * parallel submission 272 */ 273 u64 fence_context; 274 /** 275 * @seqno: seqno for composite fence when doing parallel 276 * submission 277 */ 278 u32 seqno; 279 /** @number_children: number of children if parent */ 280 u8 number_children; 281 /** @child_index: index into child_list if child */ 282 u8 child_index; 283 /** @guc: GuC specific members for parallel submission */ 284 struct { 285 /** @wqi_head: cached head pointer in work queue */ 286 u16 wqi_head; 287 /** @wqi_tail: cached tail pointer in work queue */ 288 u16 wqi_tail; 289 /** @wq_head: pointer to the actual head in work queue */ 290 u32 *wq_head; 291 /** @wq_tail: pointer to the actual head in work queue */ 292 u32 *wq_tail; 293 /** @wq_status: pointer to the status in work queue */ 294 u32 *wq_status; 295 296 /** 297 * @parent_page: page in context state (ce->state) used 298 * by parent for work queue, process descriptor 299 */ 300 u8 parent_page; 301 } guc; 302 } parallel; 303 304 #ifdef CONFIG_DRM_I915_SELFTEST 305 /** 306 * @drop_schedule_enable: Force drop of schedule enable G2H for selftest 307 */ 308 bool drop_schedule_enable; 309 310 /** 311 * @drop_schedule_disable: Force drop of schedule disable G2H for 312 * selftest 313 */ 314 bool drop_schedule_disable; 315 316 /** 317 * @drop_deregister: Force drop of deregister G2H for selftest 318 */ 319 bool drop_deregister; 320 #endif 321 }; 322 323 #endif /* __INTEL_CONTEXT_TYPES__ */ 324