| /linux-6.6.21/drivers/gpu/drm/i915/display/ |
| D | intel_de.h | 14 intel_de_read(struct drm_i915_private *i915, i915_reg_t reg) in intel_de_read()
20 intel_de_read8(struct drm_i915_private *i915, i915_reg_t reg) in intel_de_read8()
27 i915_reg_t lower_reg, i915_reg_t upper_reg) in intel_de_read64_2x32()
33 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg) in intel_de_posting_read()
39 intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val) in intel_de_write()
45 intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set) in intel_de_rmw()
51 intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg, in intel_de_wait_for_register()
58 intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg, in intel_de_wait_for_register_fw()
65 __intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg, in __intel_de_wait_for_register()
75 intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg, in intel_de_wait_for_set()
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| D | intel_dp_aux.c | 43 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); in intel_dp_aux_wait_done()
221 i915_reg_t ch_ctl, ch_data[5]; in intel_dp_aux_xfer()
519 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) in g4x_aux_ctl_reg()
536 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) in g4x_aux_data_reg()
553 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) in ilk_aux_ctl_reg()
572 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) in ilk_aux_data_reg()
591 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) in skl_aux_ctl_reg()
611 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) in skl_aux_data_reg()
631 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) in tgl_aux_ctl_reg()
654 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) in tgl_aux_data_reg()
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| D | intel_sdvo.h | 18 i915_reg_t sdvo_reg, enum pipe *pipe);
20 i915_reg_t reg, enum port port);
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| D | intel_vga.c | 18 static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915) in intel_vga_cntrl_reg()
32 i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv); in intel_vga_disable()
52 i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv); in intel_vga_redisable_power_on()
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| D | g4x_dp.h | 25 i915_reg_t dp_reg, enum port port,
28 i915_reg_t output_reg, enum port port);
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| D | intel_dmc.c | 58 i915_reg_t mmioaddr[20];
328 i915_reg_t ctl_reg, i915_reg_t htp_reg) in disable_event_handler()
340 i915_reg_t ctl_reg, i915_reg_t htp_reg) in disable_flip_queue_event()
365 i915_reg_t *ctl_reg, i915_reg_t *htp_reg) in get_flip_queue_event_regs()
396 i915_reg_t ctl_reg; in disable_all_flip_queue_events()
397 i915_reg_t htp_reg; in disable_all_flip_queue_events()
497 enum intel_dmc_id dmc_id, i915_reg_t reg) in is_dmc_evt_ctl_reg()
508 i915_reg_t reg, u32 data) in disable_dmc_evt()
1199 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; in intel_dmc_debugfs_status_show()
1227 i915_reg_t dc3co_reg; in intel_dmc_debugfs_status_show()
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| D | intel_display.h | 470 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
471 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
474 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
475 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
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| D | intel_dsb.c | 119 u32 opcode, i915_reg_t reg) in intel_dsb_prev_ins_is_write()
130 static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t reg) in intel_dsb_prev_ins_is_mmio_write()
135 static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg) in intel_dsb_prev_ins_is_indexed_write()
150 i915_reg_t reg, u32 val) in intel_dsb_reg_write()
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| D | intel_pch_display.c | 39 i915_reg_t dp_reg) in assert_pch_dp_disabled()
58 i915_reg_t hdmi_reg) in assert_pch_hdmi_disabled()
114 enum port port, i915_reg_t hdmi_reg) in ibx_sanitize_pch_hdmi_port()
133 enum port port, i915_reg_t dp_reg) in ibx_sanitize_pch_dp_port()
247 i915_reg_t reg; in ilk_enable_pch_transcoder()
313 i915_reg_t reg; in ilk_disable_pch_transcoder()
416 i915_reg_t reg = TRANS_DP_CTL(pipe); in ilk_pch_enable()
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| D | intel_ddi.h | 26 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
28 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
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| D | intel_pps.c | 472 i915_reg_t pp_ctrl;
473 i915_reg_t pp_stat;
474 i915_reg_t pp_on;
475 i915_reg_t pp_off;
476 i915_reg_t pp_div;
507 static i915_reg_t
517 static i915_reg_t
591 i915_reg_t pp_stat_reg, pp_ctrl_reg; in wait_panel_status()
720 i915_reg_t pp_stat_reg, pp_ctrl_reg; in intel_pps_vdd_on_unlocked()
802 i915_reg_t pp_stat_reg, pp_ctrl_reg; in intel_pps_vdd_off_sync_unlocked()
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| D | g4x_hdmi.h | 19 i915_reg_t hdmi_reg, enum port port);
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| D | intel_crt.h | 16 i915_reg_t adpa_reg, enum pipe *pipe);
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| D | intel_lvds.h | 17 i915_reg_t lvds_reg, enum pipe *pipe);
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| /linux-6.6.21/drivers/gpu/drm/i915/ |
| D | intel_uncore.h | 98 i915_reg_t r);
100 i915_reg_t r);
103 i915_reg_t r, bool trace);
105 i915_reg_t r, bool trace);
107 i915_reg_t r, bool trace);
109 i915_reg_t r, bool trace);
112 i915_reg_t r, u8 val, bool trace);
114 i915_reg_t r, u16 val, bool trace);
116 i915_reg_t r, u32 val, bool trace);
261 i915_reg_t reg, unsigned int op);
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| D | i915_irq.h | 43 void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg);
45 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
46 i915_reg_t iir, i915_reg_t ier);
49 i915_reg_t imr, u32 imr_val,
50 i915_reg_t ier, u32 ier_val,
51 i915_reg_t iir);
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| D | i915_perf_types.h | 50 i915_reg_t oa_head_ptr;
51 i915_reg_t oa_tail_ptr;
52 i915_reg_t oa_buffer;
53 i915_reg_t oa_ctx_ctrl;
54 i915_reg_t oa_ctrl;
55 i915_reg_t oa_debug;
56 i915_reg_t oa_status;
73 i915_reg_t addr;
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| D | i915_hwmon.c | 33 i915_reg_t gt_perf_status;
34 i915_reg_t pkg_power_sku_unit;
35 i915_reg_t pkg_power_sku;
36 i915_reg_t pkg_rapl_limit;
37 i915_reg_t energy_status_all;
38 i915_reg_t energy_status_tile;
69 i915_reg_t reg, u32 clear, u32 set) in hwm_locked_with_pm_intel_uncore_rmw()
89 hwm_field_read_and_scale(struct hwm_drvdata *ddat, i915_reg_t rgadr, in hwm_field_read_and_scale()
131 i915_reg_t rgaddr; in hwm_energy()
539 i915_reg_t rgaddr; in hwm_energy_is_visible()
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| D | i915_reg_defs.h | 265 } i915_reg_t; typedef
267 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
283 _Generic((r), i915_reg_t: (r).reg, i915_mcr_reg_t: (r).reg)
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| D | i915_ioctl.c | 23 i915_reg_t offset_ldw;
24 i915_reg_t offset_udw;
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| D | intel_uncore.c | 1212 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) in gen6_reg_write_fw_domains()
1904 const i915_reg_t reg, in __unclaimed_reg_debug()
1918 const i915_reg_t reg, in __unclaimed_previous_reg_debug()
1930 const i915_reg_t reg, const bool read) in unclaimed_reg_debug_header()
1946 const i915_reg_t reg, const bool read) in unclaimed_reg_debug_footer()
1957 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1977 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1985 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
2052 fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \
2064 fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { in fwtable_reg_read_fw_domains()
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| /linux-6.6.21/drivers/gpu/drm/i915/gt/ |
| D | intel_gt_pm_irq.c | 18 i915_reg_t reg; in write_pm_imr()
65 i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; in gen6_gt_pm_reset_iir()
79 i915_reg_t reg; in write_pm_ier()
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| D | intel_workarounds_types.h | 17 i915_reg_t reg;
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| /linux-6.6.21/drivers/gpu/drm/i915/selftests/ |
| D | mock_uncore.c | 29 nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }
36 nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }
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| D | intel_uncore.c | 212 i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset); in live_forcewake_ops()
304 i915_reg_t reg = { offset }; in live_forcewake_domains()
315 i915_reg_t reg = { offset }; in live_forcewake_domains()
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