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Searched refs:hwpwm (Results 1 – 25 of 48) sorted by relevance

12

/linux-6.6.21/drivers/pwm/
Dpwm-vt8500.c105 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); in vt8500_pwm_config()
106 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE); in vt8500_pwm_config()
108 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); in vt8500_pwm_config()
109 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE); in vt8500_pwm_config()
111 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); in vt8500_pwm_config()
112 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE); in vt8500_pwm_config()
114 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
116 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
117 vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE); in vt8500_pwm_config()
135 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_enable()
[all …]
Dpwm-jz4740.c57 if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm)) in jz4740_pwm_request()
60 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm); in jz4740_pwm_request()
92 regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN); in jz4740_pwm_enable()
95 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm)); in jz4740_pwm_enable()
108 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff); in jz4740_pwm_disable()
109 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0); in jz4740_pwm_disable()
116 regmap_clear_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN); in jz4740_pwm_disable()
119 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm)); in jz4740_pwm_disable()
177 regmap_write(jz4740->map, TCU_REG_TCNTc(pwm->hwpwm), 0); in jz4740_pwm_apply()
180 regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), duty); in jz4740_pwm_apply()
[all …]
Dpwm-sunplus.c69 mode0 &= ~SP7021_PWM_MODE0_PWMEN(pwm->hwpwm); in sunplus_pwm_apply()
73 mode1 &= ~SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm); in sunplus_pwm_apply()
101 writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm)); in sunplus_pwm_apply()
105 mode0 |= SP7021_PWM_MODE0_PWMEN(pwm->hwpwm); in sunplus_pwm_apply()
107 mode1 |= SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm); in sunplus_pwm_apply()
110 mode0 |= SP7021_PWM_MODE0_BYPASS(pwm->hwpwm); in sunplus_pwm_apply()
111 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX; in sunplus_pwm_apply()
113 mode0 &= ~SP7021_PWM_MODE0_BYPASS(pwm->hwpwm); in sunplus_pwm_apply()
119 duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty; in sunplus_pwm_apply()
121 writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm)); in sunplus_pwm_apply()
[all …]
Dpwm-sun4i.c130 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && in sun4i_pwm_get_state()
139 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && in sun4i_pwm_get_state()
143 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; in sun4i_pwm_get_state()
148 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) in sun4i_pwm_get_state()
153 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == in sun4i_pwm_get_state()
154 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) in sun4i_pwm_get_state()
159 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_get_state()
267 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
274 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
277 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { in sun4i_pwm_apply()
[all …]
Dpwm-atmel.c247 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_update_cdty()
249 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_update_cdty()
252 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_update_cdty()
254 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm); in atmel_pwm_update_cdty()
263 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
265 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
275 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm); in atmel_pwm_disable()
277 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); in atmel_pwm_disable()
285 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && in atmel_pwm_disable()
310 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_apply()
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Dpwm-sprd.c74 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_get_state()
86 pwm->hwpwm); in sprd_pwm_get_state()
90 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); in sprd_pwm_get_state()
104 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); in sprd_pwm_get_state()
109 val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); in sprd_pwm_get_state()
125 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_config()
155 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); in sprd_pwm_config()
156 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); in sprd_pwm_config()
157 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); in sprd_pwm_config()
167 struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; in sprd_pwm_apply()
[all …]
Dpwm-bcm-iproc.c80 if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
85 if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
98 prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); in iproc_pwmc_get_state()
103 value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
107 value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
155 iproc_pwmc_disable(ip, pwm->hwpwm); in iproc_pwmc_apply()
159 value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm); in iproc_pwmc_apply()
160 value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); in iproc_pwmc_apply()
164 writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_apply()
165 writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_apply()
[all …]
Dpwm-stmpe.c48 pwm->hwpwm); in stmpe_24xx_pwm_enable()
52 value = ret | BIT(pwm->hwpwm); in stmpe_24xx_pwm_enable()
57 pwm->hwpwm); in stmpe_24xx_pwm_enable()
74 pwm->hwpwm); in stmpe_24xx_pwm_disable()
78 value = ret & ~BIT(pwm->hwpwm); in stmpe_24xx_pwm_disable()
83 pwm->hwpwm); in stmpe_24xx_pwm_disable()
118 pin = pwm->hwpwm; in stmpe_24xx_pwm_config()
129 pwm->hwpwm); in stmpe_24xx_pwm_config()
135 switch (pwm->hwpwm) { in stmpe_24xx_pwm_config()
154 pwm->hwpwm, duty_ns, period_ns); in stmpe_24xx_pwm_config()
[all …]
Dpwm-bcm2835.c44 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
45 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
57 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_free()
103 writel(period_cycles, pc->base + PERIOD(pwm->hwpwm)); in bcm2835_pwm_apply()
107 writel(val, pc->base + DUTY(pwm->hwpwm)); in bcm2835_pwm_apply()
113 val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_apply()
115 val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm); in bcm2835_pwm_apply()
119 val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm); in bcm2835_pwm_apply()
121 val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_apply()
Dpwm-microchip-core.c82 reg_offset = MCHPCOREPWM_EN(pwm->hwpwm >> 3); in mchp_core_pwm_enable()
83 shift = pwm->hwpwm & 7; in mchp_core_pwm_enable()
90 mchp_core_pwm->channel_enabled &= ~BIT(pwm->hwpwm); in mchp_core_pwm_enable()
91 mchp_core_pwm->channel_enabled |= enable << pwm->hwpwm; in mchp_core_pwm_enable()
98 if (mchp_core_pwm->sync_update_mask & (1 << pwm->hwpwm)) in mchp_core_pwm_enable()
181 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
182 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
311 period_locked = mchp_core_pwm->channel_enabled & ~(1 << pwm->hwpwm); in mchp_core_pwm_apply_locked()
368 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); in mchp_core_pwm_apply()
387 mchp_core_pwm_wait_for_sync_update(mchp_core_pwm, pwm->hwpwm); in mchp_core_pwm_get_state()
[all …]
Dpwm-twl.c83 base = pwm->hwpwm * 3; in twl_pwm_config()
107 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_enable()
113 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_enable()
137 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMX_ENABLE); in twl4030_pwm_disable()
143 val &= ~TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_disable()
159 if (pwm->hwpwm == 1) { in twl4030_pwm_request()
197 if (pwm->hwpwm == 1) in twl4030_pwm_free()
229 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXS | TWL6030_PWMXEN); in twl6030_pwm_enable()
230 val &= ~TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); in twl6030_pwm_enable()
252 val |= TWL6030_PWM_TOGGLE(pwm->hwpwm, TWL6030_PWMXR); in twl6030_pwm_disable()
[all …]
Dpwm-visconti.c53 writel(0, priv->base + PIPGM_PCSR(pwm->hwpwm)); in visconti_pwm_apply()
99 writel(pwmc0, priv->base + PIPGM_PWMC(pwm->hwpwm)); in visconti_pwm_apply()
100 writel(duty_cycle, priv->base + PIPGM_PDUT(pwm->hwpwm)); in visconti_pwm_apply()
101 writel(period, priv->base + PIPGM_PCSR(pwm->hwpwm)); in visconti_pwm_apply()
112 period = readl(priv->base + PIPGM_PCSR(pwm->hwpwm)); in visconti_pwm_get_state()
113 duty = readl(priv->base + PIPGM_PDUT(pwm->hwpwm)); in visconti_pwm_get_state()
114 pwmc0 = readl(priv->base + PIPGM_PWMC(pwm->hwpwm)); in visconti_pwm_get_state()
Dpwm-rz-mtu3.c134 rz_mtu3_get_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm) in rz_mtu3_get_channel() argument
140 if (priv->map->base_pwm_number + priv->map->num_channel_ios > hwpwm) in rz_mtu3_get_channel()
148 u32 hwpwm) in rz_mtu3_pwm_is_ch_enabled() argument
154 priv = rz_mtu3_get_channel(rz_mtu3_pwm, hwpwm); in rz_mtu3_pwm_is_ch_enabled()
159 if (priv->map->base_pwm_number == hwpwm) in rz_mtu3_pwm_is_ch_enabled()
174 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_request()
203 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_free()
226 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_enable()
231 if (priv->map->base_pwm_number == pwm->hwpwm) in rz_mtu3_pwm_enable()
252 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_disable()
[all …]
Dpwm-berlin.c116 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_CONTROL); in berlin_pwm_config()
121 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_CONTROL); in berlin_pwm_config()
123 berlin_pwm_writel(bpc, pwm->hwpwm, duty, BERLIN_PWM_DUTY); in berlin_pwm_config()
124 berlin_pwm_writel(bpc, pwm->hwpwm, period, BERLIN_PWM_TCNT); in berlin_pwm_config()
136 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_CONTROL); in berlin_pwm_set_polarity()
143 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_CONTROL); in berlin_pwm_set_polarity()
153 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_EN); in berlin_pwm_enable()
155 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_EN); in berlin_pwm_enable()
166 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_EN); in berlin_pwm_disable()
168 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_EN); in berlin_pwm_disable()
Dpwm-lpc18xx-sct.c142 val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm); in lpc18xx_pwm_set_conflict_res()
143 val |= LPC18XX_PWM_RES(pwm->hwpwm, action); in lpc18xx_pwm_set_conflict_res()
175 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; in lpc18xx_pwm_config_duty()
218 pwm->hwpwm); in lpc18xx_pwm_config()
241 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; in lpc18xx_pwm_enable()
264 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), in lpc18xx_pwm_enable()
266 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), in lpc18xx_pwm_enable()
276 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm]; in lpc18xx_pwm_disable()
280 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0); in lpc18xx_pwm_disable()
281 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 0); in lpc18xx_pwm_disable()
[all …]
Dpwm-dwc.c116 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); in __dwc_pwm_configure_timer()
124 dwc_pwm_writel(dwc, low, DWC_TIM_LD_CNT(pwm->hwpwm)); in __dwc_pwm_configure_timer()
125 dwc_pwm_writel(dwc, high, DWC_TIM_LD_CNT2(pwm->hwpwm)); in __dwc_pwm_configure_timer()
134 dwc_pwm_writel(dwc, ctrl, DWC_TIM_CTRL(pwm->hwpwm)); in __dwc_pwm_configure_timer()
139 __dwc_pwm_set_enable(dwc, pwm->hwpwm, state->enabled); in __dwc_pwm_configure_timer()
158 __dwc_pwm_set_enable(dwc, pwm->hwpwm, false); in dwc_pwm_apply()
175 DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); in dwc_pwm_get_state()
177 duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); in dwc_pwm_get_state()
182 period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); in dwc_pwm_get_state()
Dpwm-hibvt.c87 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
95 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
110 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), in hibvt_pwm_config()
113 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), in hibvt_pwm_config()
124 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
127 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
141 value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
144 value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
147 value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm)); in hibvt_pwm_get_state()
Dpwm-sti.c192 ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) || in sti_pwm_config()
193 ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) || in sti_pwm_config()
230 ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value); in sti_pwm_config()
236 set_bit(pwm->hwpwm, &pc->configured); in sti_pwm_config()
275 pwm->hwpwm, ret); in sti_pwm_enable()
310 clear_bit(pwm->hwpwm, &pc->configured); in sti_pwm_free()
318 struct sti_cpt_ddata *ddata = &cdata->ddata[pwm->hwpwm]; in sti_pwm_capture()
324 if (pwm->hwpwm >= cdata->cpt_num_devs) { in sti_pwm_capture()
325 dev_err(dev, "device %u is not valid\n", pwm->hwpwm); in sti_pwm_capture()
333 regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING); in sti_pwm_capture()
[all …]
Dpwm-mediatek.c90 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_clk_enable()
109 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_clk_disable()
141 do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm])); in pwm_mediatek_config()
157 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { in pwm_mediatek_config()
167 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); in pwm_mediatek_config()
168 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); in pwm_mediatek_config()
169 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); in pwm_mediatek_config()
187 value |= BIT(pwm->hwpwm); in pwm_mediatek_enable()
199 value &= ~BIT(pwm->hwpwm); in pwm_mediatek_disable()
Dpwm-spear.c128 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, in spear_pwm_config()
130 spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc); in spear_pwm_config()
131 spear_pwm_writel(pc, pwm->hwpwm, PWMPCR, pv); in spear_pwm_config()
147 val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); in spear_pwm_enable()
149 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); in spear_pwm_enable()
159 val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); in spear_pwm_disable()
161 spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); in spear_pwm_disable()
Dpwm-samsung.c123 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in __pwm_samsung_manual_update()
233 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { in pwm_samsung_request()
236 pwm->hwpwm); in pwm_samsung_request()
257 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in pwm_samsung_enable()
273 our_chip->disabled_mask &= ~BIT(pwm->hwpwm); in pwm_samsung_enable()
283 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in pwm_samsung_disable()
297 if (readl(our_chip->base + REG_TCMPB(pwm->hwpwm)) == (u32)-1U) in pwm_samsung_disable()
300 our_chip->disabled_mask |= BIT(pwm->hwpwm); in pwm_samsung_disable()
324 tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm)); in __pwm_samsung_config()
325 oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm)); in __pwm_samsung_config()
[all …]
Dpwm-pca9685.c381 pca9685_pwm_set_duty(pca, pwm->hwpwm, 0); in __pca9685_pwm_apply()
387 if (!pca9685_prescaler_can_change(pca, pwm->hwpwm)) { in __pca9685_pwm_apply()
411 pca9685_pwm_set_duty(pca, pwm->hwpwm, duty); in __pca9685_pwm_apply()
425 set_bit(pwm->hwpwm, pca->pwms_enabled); in pca9685_pwm_apply()
427 clear_bit(pwm->hwpwm, pca->pwms_enabled); in pca9685_pwm_apply()
454 if (pwm->hwpwm >= PCA9685_MAXCHAN) { in pca9685_pwm_get_state()
465 duty = pca9685_pwm_get_duty(pca, pwm->hwpwm); in pca9685_pwm_get_state()
475 if (pca9685_pwm_test_and_set_inuse(pca, pwm->hwpwm)) in pca9685_pwm_request()
478 if (pwm->hwpwm < PCA9685_MAXCHAN) { in pca9685_pwm_request()
481 set_bit(pwm->hwpwm, pca->pwms_enabled); in pca9685_pwm_request()
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Dsysfs.c263 dev_set_name(&export->child, "pwm%u", pwm->hwpwm); in pwm_export_child()
272 pwm_prop[0] = kasprintf(GFP_KERNEL, "EXPORT=pwm%u", pwm->hwpwm); in pwm_export_child()
297 pwm_prop[0] = kasprintf(GFP_KERNEL, "UNEXPORT=pwm%u", pwm->hwpwm); in pwm_unexport_child()
316 unsigned int hwpwm; in export_store() local
319 ret = kstrtouint(buf, 0, &hwpwm); in export_store()
323 if (hwpwm >= chip->npwm) in export_store()
326 pwm = pwm_request_from_chip(chip, hwpwm, "sysfs"); in export_store()
343 unsigned int hwpwm; in unexport_store() local
346 ret = kstrtouint(buf, 0, &hwpwm); in unexport_store()
350 if (hwpwm >= chip->npwm) in unexport_store()
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Dpwm-keembay.c103 highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); in keembay_pwm_get_state()
110 highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm)); in keembay_pwm_get_state()
138 KMB_PWM_LEADIN_OFFSET(pwm->hwpwm)); in keembay_pwm_apply()
144 keembay_pwm_disable(priv, pwm->hwpwm); in keembay_pwm_apply()
172 writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm)); in keembay_pwm_apply()
175 keembay_pwm_enable(priv, pwm->hwpwm); in keembay_pwm_apply()
Dpwm-stm32.c122 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; in stm32_pwm_raw_capture()
123 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; in stm32_pwm_raw_capture()
124 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; in stm32_pwm_raw_capture()
216 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, in stm32_pwm_capture()
217 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ? in stm32_pwm_capture()
222 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ? in stm32_pwm_capture()
223 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ? in stm32_pwm_capture()
270 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, in stm32_pwm_capture()
316 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0); in stm32_pwm_capture()
457 stm32_pwm_disable(priv, pwm->hwpwm); in stm32_pwm_apply()
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