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Searched refs:hart (Results 1 – 13 of 13) sorted by relevance

/linux-6.6.21/arch/riscv/kernel/
Dcpu.c29 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument
33 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
34 if (*hart == ~0UL) { in riscv_of_processor_hartid()
39 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
49 int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_early_of_processor_hartid() argument
58 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_early_of_processor_hartid()
59 if (*hart == ~0UL) { in riscv_early_of_processor_hartid()
65 pr_info("CPU with hartid=%lu is not available\n", *hart); in riscv_early_of_processor_hartid()
73 pr_warn("CPU with hartid=%lu does not support rv32i", *hart); in riscv_early_of_processor_hartid()
78 pr_warn("CPU with hartid=%lu does not support rv64i", *hart); in riscv_early_of_processor_hartid()
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Dsmpboot.c82 unsigned long hart; in acpi_parse_rintc() local
99 hart = processor->hart_id; in acpi_parse_rintc()
100 if (hart == INVALID_HARTID) { in acpi_parse_rintc()
105 if (hart == cpuid_to_hartid_map(0)) { in acpi_parse_rintc()
117 cpuid_to_hartid_map(cpu_count) = hart; in acpi_parse_rintc()
146 unsigned long hart; in of_parse_and_init_cpus() local
154 rc = riscv_early_of_processor_hartid(dn, &hart); in of_parse_and_init_cpus()
158 if (hart == cpuid_to_hartid_map(0)) { in of_parse_and_init_cpus()
166 cpuid, hart); in of_parse_and_init_cpus()
170 cpuid_to_hartid_map(cpuid) = hart; in of_parse_and_init_cpus()
/linux-6.6.21/Documentation/devicetree/bindings/riscv/
Dcpus.yaml18 hart: A hardware execution context, which contains all the state
59 Identifies that the hart uses the RISC-V instruction set
60 and identifies the type of the hart.
65 hart. These values originate from the RISC-V Privileged
117 by this hart (see ./idle-states.yaml).
Dextensions.yaml18 This document defines properties that indicate whether a hart supports a
37 supported by the hart. These are documented in the RISC-V
56 The base ISA implemented by this hart, as described by the 20191213
65 description: Extensions supported by the hart.
/linux-6.6.21/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
40 definition of the hart whose CSRs control these local interrupts.
Dsifive,plic-1.0.0.yaml14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
17 A hart context is a privilege mode in a hardware execution thread. For example,
19 privilege modes per hart; machine mode and supervisor mode.
/linux-6.6.21/tools/perf/pmu-events/arch/riscv/
Dmapfile.csv6 # MARCHID base microarchitecture of the hart
/linux-6.6.21/arch/riscv/kvm/
Daia_device.c240 u32 hart, group = 0; in aia_imsic_hart_index() local
242 hart = (addr >> (aia->nr_guest_bits + IMSIC_MMIO_PAGE_SHIFT)) & in aia_imsic_hart_index()
248 return (group << aia->nr_hart_bits) | hart; in aia_imsic_hart_index()
/linux-6.6.21/Documentation/riscv/
Dboot.rst68 - ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart
72 - ``Ordered booting``: the firmware releases only one hart that will execute the
/linux-6.6.21/Documentation/devicetree/bindings/iio/addac/
Dadi,ad74115.yaml188 adi,dac-hart-slew:
/linux-6.6.21/arch/riscv/
DKconfig664 Since spinwait is incompatible with sparse hart IDs, it requires
665 NR_CPUS be large enough to contain the physical hart ID of the first
666 hart to enter Linux.
/linux-6.6.21/Documentation/devicetree/bindings/cpu/
Didle-states.yaml57 RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
60 The platform specific suspend (or idle) states of a hart can be either
/linux-6.6.21/drivers/clocksource/
DKconfig640 This enables the per-hart timer built into all RISC-V systems, which