| /linux-6.6.21/drivers/gpu/drm/mediatek/ |
| D | mtk_drm_ddp_comp.h | 89 const struct mtk_ddp_comp_funcs *funcs; member
94 if (comp->funcs && comp->funcs->clk_enable) in mtk_ddp_comp_clk_enable()
95 return comp->funcs->clk_enable(comp->dev); in mtk_ddp_comp_clk_enable()
102 if (comp->funcs && comp->funcs->clk_disable) in mtk_ddp_comp_clk_disable()
103 comp->funcs->clk_disable(comp->dev); in mtk_ddp_comp_clk_disable()
111 if (comp->funcs && comp->funcs->config) in mtk_ddp_comp_config()
112 comp->funcs->config(comp->dev, w, h, vrefresh, bpc, cmdq_pkt); in mtk_ddp_comp_config()
117 if (comp->funcs && comp->funcs->start) in mtk_ddp_comp_start()
118 comp->funcs->start(comp->dev); in mtk_ddp_comp_start()
123 if (comp->funcs && comp->funcs->stop) in mtk_ddp_comp_stop()
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| /linux-6.6.21/drivers/gpu/drm/ |
| D | drm_simple_kms_helper.c | 92 if (!pipe->funcs || !pipe->funcs->mode_valid) in drm_simple_kms_crtc_mode_valid()
96 return pipe->funcs->mode_valid(pipe, mode); in drm_simple_kms_crtc_mode_valid()
123 if (!pipe->funcs || !pipe->funcs->enable) in drm_simple_kms_crtc_enable()
127 pipe->funcs->enable(pipe, crtc->state, plane->state); in drm_simple_kms_crtc_enable()
136 if (!pipe->funcs || !pipe->funcs->disable) in drm_simple_kms_crtc_disable()
139 pipe->funcs->disable(pipe); in drm_simple_kms_crtc_disable()
154 if (!pipe->funcs || !pipe->funcs->reset_crtc) in drm_simple_kms_crtc_reset()
157 return pipe->funcs->reset_crtc(pipe); in drm_simple_kms_crtc_reset()
165 if (!pipe->funcs || !pipe->funcs->duplicate_crtc_state) in drm_simple_kms_crtc_duplicate_state()
168 return pipe->funcs->duplicate_crtc_state(pipe); in drm_simple_kms_crtc_duplicate_state()
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| D | drm_bridge.c | 259 state = bridge->funcs->atomic_duplicate_state(bridge); in drm_bridge_atomic_duplicate_priv_state()
270 bridge->funcs->atomic_destroy_state(bridge, state); in drm_bridge_atomic_destroy_priv_state()
324 if (bridge->funcs->attach) { in drm_bridge_attach()
325 ret = bridge->funcs->attach(bridge, flags); in drm_bridge_attach()
330 if (bridge->funcs->atomic_reset) { in drm_bridge_attach()
333 state = bridge->funcs->atomic_reset(bridge); in drm_bridge_attach()
347 if (bridge->funcs->detach) in drm_bridge_attach()
348 bridge->funcs->detach(bridge); in drm_bridge_attach()
375 if (bridge->funcs->atomic_reset) in drm_bridge_detach()
378 if (bridge->funcs->detach) in drm_bridge_detach()
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| D | drm_panel.c | 58 const struct drm_panel_funcs *funcs, int connector_type) in drm_panel_init() argument
64 panel->funcs = funcs; in drm_panel_init()
123 if (panel->funcs && panel->funcs->prepare) { in drm_panel_prepare()
124 ret = panel->funcs->prepare(panel); in drm_panel_prepare()
131 ret = follower->funcs->panel_prepared(follower); in drm_panel_prepare()
134 follower->funcs->panel_prepared, ret); in drm_panel_prepare()
172 ret = follower->funcs->panel_unpreparing(follower); in drm_panel_unprepare()
175 follower->funcs->panel_unpreparing, ret); in drm_panel_unprepare()
178 if (panel->funcs && panel->funcs->unprepare) { in drm_panel_unprepare()
179 ret = panel->funcs->unprepare(panel); in drm_panel_unprepare()
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| D | drm_atomic_helper.c | 120 const struct drm_connector_helper_funcs *funcs = connector->helper_private; in handle_conflicting_encoders() local
126 if (funcs->atomic_best_encoder) in handle_conflicting_encoders()
127 new_encoder = funcs->atomic_best_encoder(connector, in handle_conflicting_encoders()
129 else if (funcs->best_encoder) in handle_conflicting_encoders()
130 new_encoder = funcs->best_encoder(connector); in handle_conflicting_encoders()
296 const struct drm_connector_helper_funcs *funcs; in update_connector_routing() local
356 funcs = connector->helper_private; in update_connector_routing()
358 if (funcs->atomic_best_encoder) in update_connector_routing()
359 new_encoder = funcs->atomic_best_encoder(connector, state); in update_connector_routing()
360 else if (funcs->best_encoder) in update_connector_routing()
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| D | drm_encoder.c | 77 if (encoder->funcs && encoder->funcs->late_register) in drm_encoder_register_all()
78 ret = encoder->funcs->late_register(encoder); in drm_encoder_register_all()
91 if (encoder->funcs && encoder->funcs->early_unregister) in drm_encoder_unregister_all()
92 encoder->funcs->early_unregister(encoder); in drm_encoder_unregister_all()
99 const struct drm_encoder_funcs *funcs, in __drm_encoder_init() argument
114 encoder->funcs = funcs; in __drm_encoder_init()
161 const struct drm_encoder_funcs *funcs, in drm_encoder_init() argument
167 WARN_ON(!funcs->destroy); in drm_encoder_init()
170 ret = __drm_encoder_init(dev, encoder, funcs, encoder_type, name, ap); in drm_encoder_init()
219 const struct drm_encoder_funcs *funcs, in __drmm_encoder_init() argument
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| D | drm_client.c | 80 const char *name, const struct drm_client_funcs *funcs) in drm_client_init() argument
87 if (funcs && !try_module_get(funcs->owner)) in drm_client_init()
92 client->funcs = funcs; in drm_client_init()
109 if (funcs) in drm_client_init()
110 module_put(funcs->owner); in drm_client_init()
138 if (client->funcs && client->funcs->hotplug) { in drm_client_register()
149 ret = client->funcs->hotplug(client); in drm_client_register()
180 if (client->funcs) in drm_client_release()
181 module_put(client->funcs->owner); in drm_client_release()
195 if (client->funcs && client->funcs->unregister) { in drm_client_dev_unregister()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hwseq.c | 92 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode) in enable_memory_low_power()
93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
96 …if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerd… in enable_memory_low_power()
99 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); in enable_memory_low_power()
102 …dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->… in enable_memory_low_power()
117 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) in dcn31_init_hw()
118 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); in dcn31_init_hw()
120 if (!dcb->funcs->is_accelerated_mode(dcb)) { in dcn31_init_hw()
121 hws->funcs.bios_golden_init(dc); in dcn31_init_hw()
122 if (hws->funcs.disable_vga) in dcn31_init_hw()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_srv.c | 154 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; in dmub_srv_hw_setup() local
165 funcs->reset = dmub_dcn20_reset; in dmub_srv_hw_setup()
166 funcs->reset_release = dmub_dcn20_reset_release; in dmub_srv_hw_setup()
167 funcs->backdoor_load = dmub_dcn20_backdoor_load; in dmub_srv_hw_setup()
168 funcs->setup_windows = dmub_dcn20_setup_windows; in dmub_srv_hw_setup()
169 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; in dmub_srv_hw_setup()
170 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; in dmub_srv_hw_setup()
171 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; in dmub_srv_hw_setup()
172 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; in dmub_srv_hw_setup()
173 funcs->is_supported = dmub_dcn20_is_supported; in dmub_srv_hw_setup()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.c | 166 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && in dcn20_setup_gsl_group_as_lock()
167 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { in dcn20_setup_gsl_group_as_lock()
168 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
172 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
182 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) in dcn20_set_flip_control_gsl()
183 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( in dcn20_set_flip_control_gsl()
278 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_triple_buffer()
279 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( in dcn20_program_triple_buffer()
303 tg->funcs->get_otg_active_size(tg, in dcn20_init_blank()
308 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); in dcn20_init_blank()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.c | 114 !tg->funcs->is_tg_enabled(tg) || in dcn10_lock_all_pipes()
147 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
180 hubp->funcs->hubp_read_state(hubp); in dcn10_log_hubp_states()
302 dpp->funcs->dpp_read_state(dpp, &s); in dcn10_log_hw_state()
343 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s); in dcn10_log_hw_state()
367 if (pool->opps[i]->funcs->dpg_is_blanked) in dcn10_log_hw_state()
368 s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]); in dcn10_log_hw_state()
370 s.blank_enabled = tg->funcs->is_blanked(tg); in dcn10_log_hw_state()
401 tg->funcs->clear_optc_underflow(tg); in dcn10_log_hw_state()
412 dsc->funcs->dsc_read_state(dsc, &s); in dcn10_log_hw_state()
[all …]
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| /linux-6.6.21/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ib.c | 179 (!ring->funcs->secure_submission_supported)) { in amdgpu_ib_schedule()
184 alloc_size = ring->funcs->emit_frame_size + num_ibs * in amdgpu_ib_schedule()
185 ring->funcs->emit_ib_size; in amdgpu_ib_schedule()
194 if (ring->funcs->emit_pipeline_sync && job && in amdgpu_ib_schedule()
206 if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) in amdgpu_ib_schedule()
207 ring->funcs->emit_mem_sync(ring); in amdgpu_ib_schedule()
209 if (ring->funcs->emit_wave_limit && in amdgpu_ib_schedule()
211 ring->funcs->emit_wave_limit(ring, true); in amdgpu_ib_schedule()
213 if (ring->funcs->insert_start) in amdgpu_ib_schedule()
214 ring->funcs->insert_start(ring); in amdgpu_ib_schedule()
[all …]
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| D | amdgpu_psp.h | 316 const struct psp_funcs *funcs; member
402 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
403 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
404 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
406 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
408 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
410 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
412 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
414 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
416 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
[all …]
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| D | amdgpu_display.h | 26 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((…
27 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level…
28 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e…
29 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
30 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), …
31 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
32 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
33 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev)…
34 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page…
35 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e),…
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| D | amdgpu_ring.c | 85 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; in amdgpu_ring_alloc()
96 if (ring->funcs->begin_use) in amdgpu_ring_alloc()
97 ring->funcs->begin_use(ring); in amdgpu_ring_alloc()
114 amdgpu_ring_write(ring, ring->funcs->nop); in amdgpu_ring_insert_nop()
127 while (ib->length_dw & ring->funcs->align_mask) in amdgpu_ring_generic_pad_ib()
128 ib->ptr[ib->length_dw++] = ring->funcs->nop; in amdgpu_ring_generic_pad_ib()
145 count = ring->funcs->align_mask + 1 - in amdgpu_ring_commit()
146 (ring->wptr & ring->funcs->align_mask); in amdgpu_ring_commit()
147 count %= ring->funcs->align_mask + 1; in amdgpu_ring_commit()
148 ring->funcs->insert_nop(ring, count); in amdgpu_ring_commit()
[all …]
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| D | amdgpu_ring.h | 240 const struct amdgpu_ring_funcs *funcs; member
305 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
306 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib…
307 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
308 #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0)
309 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
310 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
311 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
312 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
313 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
[all …]
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| /linux-6.6.21/lib/ |
| D | test_min_heap.c | 34 const struct min_heap_callbacks *funcs) in pop_verify_heap() argument
41 min_heap_pop(heap, funcs); in pop_verify_heap()
57 min_heap_pop(heap, funcs); in pop_verify_heap()
71 struct min_heap_callbacks funcs = { in test_heapify_all() local
79 min_heapify_all(&heap, &funcs); in test_heapify_all()
80 err = pop_verify_heap(min_heap, &heap, &funcs); in test_heapify_all()
88 min_heapify_all(&heap, &funcs); in test_heapify_all()
89 err += pop_verify_heap(min_heap, &heap, &funcs); in test_heapify_all()
104 struct min_heap_callbacks funcs = { in test_heap_push() local
113 min_heap_push(&heap, &data[i], &funcs); in test_heap_push()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| D | link_hwss_dio.c | 34 stream_encoder->funcs->set_throttled_vcp_size( in set_dio_throttled_vcp_size()
44 link_enc->funcs->connect_dig_be_to_fe(link_enc, in setup_dio_stream_encoder()
49 if (stream_enc->funcs->map_stream_to_link) in setup_dio_stream_encoder()
50 stream_enc->funcs->map_stream_to_link(stream_enc, in setup_dio_stream_encoder()
52 if (stream_enc->funcs->enable_fifo) in setup_dio_stream_encoder()
53 stream_enc->funcs->enable_fifo(stream_enc); in setup_dio_stream_encoder()
61 if (stream_enc && stream_enc->funcs->disable_fifo) in reset_dio_stream_encoder()
62 stream_enc->funcs->disable_fifo(stream_enc); in reset_dio_stream_encoder()
64 link_enc->funcs->connect_dig_be_to_fe( in reset_dio_stream_encoder()
82 stream_encoder->funcs->setup_stereo_sync( in setup_dio_stream_attribute()
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| D | link_hwss_hpo_dp.c | 39 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(hpo_dp_link_encoder, in set_hpo_dp_throttled_vcp_size()
68 hpo_dp_stream_encoder->funcs->set_hblank_min_symbol_width(hpo_dp_stream_encoder, in set_hpo_dp_hblank_min_symbol_width()
77 stream_enc->funcs->enable_stream(stream_enc); in setup_hpo_dp_stream_encoder()
78 stream_enc->funcs->map_stream_to_link(stream_enc, stream_enc->inst, link_enc->inst); in setup_hpo_dp_stream_encoder()
85 stream_enc->funcs->disable(stream_enc); in reset_hpo_dp_stream_encoder()
94 stream_enc->funcs->set_stream_attribute( in setup_hpo_dp_stream_attribute()
111 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in enable_hpo_dp_link_output()
112 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in enable_hpo_dp_link_output()
116 link_res->hpo_dp_link_enc->funcs->enable_link_phy( in enable_hpo_dp_link_output()
127 link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc); in disable_hpo_dp_link_output()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_hwseq.c | 146 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( in dcn201_update_plane_addr()
177 tg->funcs->get_otg_active_size(tg, in dcn201_init_blank()
182 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); in dcn201_init_blank()
186 opp->funcs->opp_set_disp_pattern_generator( in dcn201_init_blank()
196 hws->funcs.wait_for_blank_complete(opp); in dcn201_init_blank()
228 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
229 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
231 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) in dcn201_init_hw()
232 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); in dcn201_init_hw()
234 hws->funcs.bios_golden_init(dc); in dcn201_init_hw()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 224 bp_result = dcb->funcs->enable_disp_power_gating( in dce110_enable_display_power_gating()
293 ipp->funcs->ipp_program_prescale(ipp, &prescale_params); in dce110_set_input_transfer_func()
298 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); in dce110_set_input_transfer_func()
302 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); in dce110_set_input_transfer_func()
306 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); in dce110_set_input_transfer_func()
309 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); in dce110_set_input_transfer_func()
312 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); in dce110_set_input_transfer_func()
320 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); in dce110_set_input_transfer_func()
611 xfm->funcs->opp_power_on_regamma_lut(xfm, true); in dce110_set_output_transfer_func()
617 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); in dce110_set_output_transfer_func()
[all …]
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_hwseq.c | 402 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); in dcn32_subvp_pipe_control_lock()
463 result = mpc->funcs->program_3dlut(mpc, in dcn32_set_mpc_shaper_3dlut()
467 result = mpc->funcs->program_shaper(mpc, in dcn32_set_mpc_shaper_3dlut()
494 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); in dcn32_set_mcm_luts()
509 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); in dcn32_set_mcm_luts()
513 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); in dcn32_set_mcm_luts()
515 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); in dcn32_set_mcm_luts()
541 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn32_set_input_transfer_func()
552 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); in dcn32_set_input_transfer_func()
556 hws->funcs.set_mcm_luts) in dcn32_set_input_transfer_func()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.c | 88 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn30_set_blend_lut()
129 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, in dcn30_set_mpc_shaper_3dlut()
134 result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, in dcn30_set_mpc_shaper_3dlut()
136 result = mpc->funcs->program_shaper(mpc, shaper_lut, in dcn30_set_mpc_shaper_3dlut()
140 mpc->funcs->release_rmu(mpc, mpcc_id); in dcn30_set_mpc_shaper_3dlut()
165 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn30_set_input_transfer_func()
176 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); in dcn30_set_input_transfer_func()
179 if (dpp_base->funcs->dpp_program_blnd_lut) in dcn30_set_input_transfer_func()
180 hws->funcs.set_blend_lut(pipe_ctx, plane_state); in dcn30_set_input_transfer_func()
181 if (dpp_base->funcs->dpp_program_shaper_lut && in dcn30_set_input_transfer_func()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/ |
| D | dc_edid_parser.c | 38 dmcu->funcs->is_dmcu_initialized(dmcu) && in dc_edid_parser_send_cea()
39 dmcu->funcs->send_edid_cea) { in dc_edid_parser_send_cea()
40 return dmcu->funcs->send_edid_cea(dmcu, in dc_edid_parser_send_cea()
55 dmcu->funcs->is_dmcu_initialized(dmcu) && in dc_edid_parser_recv_cea_ack()
56 dmcu->funcs->recv_edid_cea_ack) { in dc_edid_parser_recv_cea_ack()
57 return dmcu->funcs->recv_edid_cea_ack(dmcu, offset); in dc_edid_parser_recv_cea_ack()
71 dmcu->funcs->is_dmcu_initialized(dmcu) && in dc_edid_parser_recv_amd_vsdb()
72 dmcu->funcs->recv_amd_vsdb) { in dc_edid_parser_recv_amd_vsdb()
73 return dmcu->funcs->recv_amd_vsdb(dmcu, in dc_edid_parser_recv_amd_vsdb()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_hwseq.c | 121 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
122 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
127 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
128 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); in update_dsc_on_stream()
137 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in update_dsc_on_stream()
143 pipe_ctx->stream_res.tg->funcs->set_dsc_config( in update_dsc_on_stream()
148 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); in update_dsc_on_stream()
151 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
194 pipe_ctx->stream_res.tg->funcs->set_odm_combine( in dcn314_update_odm()
199 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( in dcn314_update_odm()
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