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Searched refs:dpp_base (Results 1 – 16 of 16) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp_cm.c51 struct dpp *dpp_base) in dpp2_enable_cm_block() argument
53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block()
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse() argument
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse()
86 struct dpp *dpp_base, in dpp2_program_degamma_lut() argument
93 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_program_degamma_lut()
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl() argument
122 dpp1_power_on_degamma_lut(dpp_base, true); in dpp2_set_degamma_pwl()
123 dpp2_enable_cm_block(dpp_base); in dpp2_set_degamma_pwl()
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Ddcn20_dpp.c51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state() argument
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state()
76 struct dpp *dpp_base, in dpp2_power_on_obuf() argument
79 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf()
91 struct dpp *dpp_base, in dpp2_dummy_program_input_lut() argument
96 struct dpp *dpp_base, in dpp2_cnv_setup() argument
103 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup()
242 dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry); in dpp2_cnv_setup()
244 dpp2_program_input_csc(dpp_base, color_space, select, NULL); in dpp2_cnv_setup()
253 dpp2_power_on_obuf(dpp_base, true); in dpp2_cnv_setup()
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Ddcn20_hwseq.c891 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_blend_lut() local
901 &dpp_base->regamma_params, false); in dcn20_set_blend_lut()
902 blend_lut = &dpp_base->regamma_params; in dcn20_set_blend_lut()
905 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn20_set_blend_lut()
913 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_shaper_3dlut() local
923 &dpp_base->shaper_params, true); in dcn20_set_shaper_3dlut()
924 shaper_lut = &dpp_base->shaper_params; in dcn20_set_shaper_3dlut()
928 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); in dcn20_set_shaper_3dlut()
931 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, in dcn20_set_shaper_3dlut()
934 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); in dcn20_set_shaper_3dlut()
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Ddcn20_dpp.h709 void dpp20_read_state(struct dpp *dpp_base,
713 struct dpp *dpp_base,
717 struct dpp *dpp_base,
721 struct dpp *dpp_base,
725 struct dpp *dpp_base,
731 struct dpp *dpp_base, const struct pwl_params *params);
734 struct dpp *dpp_base,
738 struct dpp *dpp_base,
742 struct dpp *dpp_base,
752 struct dpp *dpp_base,
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dpp.c44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp30_read_state() argument
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_read_state()
55 struct dpp *dpp_base, in dpp3_program_post_csc() argument
60 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_post_csc()
128 void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr) in dpp3_set_pre_degam() argument
130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_set_pre_degam()
171 struct dpp *dpp_base, in dpp3_cnv_setup() argument
178 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_cnv_setup()
335 dpp3_program_post_csc(dpp_base, color_space, select, in dpp3_cnv_setup()
338 dpp3_program_post_csc(dpp_base, color_space, select, NULL); in dpp3_cnv_setup()
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Ddcn30_dpp_cm.c44 struct dpp *dpp_base) in dpp3_enable_cm_block() argument
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block()
51 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp3_enable_cm_block()
57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current() argument
62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current()
81 struct dpp *dpp_base, in dpp3_program_gammcor_lut() argument
87 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_gammcor_lut()
130 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut() argument
133 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_power_on_gamcor_lut()
135 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { in dpp3_power_on_gamcor_lut()
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Ddcn30_hwseq.c75 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut() local
84 plane_state->blend_tf, &dpp_base->regamma_params, false); in dcn30_set_blend_lut()
85 blend_lut = &dpp_base->regamma_params; in dcn30_set_blend_lut()
88 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn30_set_blend_lut()
96 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut() local
110 &dpp_base->shaper_params, true); in dcn30_set_mpc_shaper_3dlut()
111 shaper_lut = &dpp_base->shaper_params; in dcn30_set_mpc_shaper_3dlut()
151 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func() local
156 if (dpp_base == NULL || plane_state == NULL) in dcn30_set_input_transfer_func()
165 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn30_set_input_transfer_func()
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Ddcn30_dpp.h587 struct dpp *dpp_base, const struct pwl_params *params);
590 struct dpp *dpp_base,
593 void dpp30_read_state(struct dpp *dpp_base,
602 struct dpp *dpp_base,
610 struct dpp *dpp_base,
614 struct dpp *dpp_base,
618 struct dpp *dpp_base,
621 void dpp3_set_pre_degam(struct dpp *dpp_base,
625 struct dpp *dpp_base,
629 struct dpp *dpp_base,
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_cm.c161 struct dpp *dpp_base, in dpp1_cm_set_gamut_remap() argument
164 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_gamut_remap()
240 struct dpp *dpp_base, in dpp1_cm_set_output_csc_default() argument
243 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_default()
310 struct dpp *dpp_base, in dpp1_cm_set_output_csc_adjustment() argument
313 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_adjustment()
318 void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, in dpp1_cm_power_on_regamma_lut() argument
321 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_power_on_regamma_lut()
328 void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, in dpp1_cm_program_regamma_lut() argument
333 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_program_regamma_lut()
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Ddcn10_dpp.c94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state() argument
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_read_state()
188 void dpp_reset(struct dpp *dpp_base) in dpp_reset() argument
190 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_reset()
204 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) in dpp1_cm_set_regamma_pwl() argument
206 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_regamma_pwl()
224 dpp1_cm_power_on_regamma_lut(dpp_base, true); in dpp1_cm_set_regamma_pwl()
225 dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); in dpp1_cm_set_regamma_pwl()
228 dpp1_cm_program_regamma_luta_settings(dpp_base, params); in dpp1_cm_set_regamma_pwl()
230 dpp1_cm_program_regamma_lutb_settings(dpp_base, params); in dpp1_cm_set_regamma_pwl()
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Ddcn10_dpp_dscl.c124 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode() argument
130 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_get_dscl_mode()
158 struct dpp *dpp_base, in dpp1_power_on_dscl() argument
161 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl()
613 void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base, in dpp1_dscl_set_scaler_manual_scale() argument
617 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_dscl_set_scaler_manual_scale()
619 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); in dpp1_dscl_set_scaler_manual_scale()
630 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) { in dpp1_dscl_set_scaler_manual_scale()
632 dpp1_power_on_dscl(dpp_base, true); in dpp1_dscl_set_scaler_manual_scale()
659 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) in dpp1_dscl_set_scaler_manual_scale()
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Ddcn10_dpp.h1382 struct dpp *dpp_base,
1386 struct dpp *dpp_base,
1393 struct dpp *dpp_base,
1408 struct dpp *dpp_base,
1412 struct dpp *dpp_base,
1416 struct dpp *dpp_base,
1420 struct dpp *dpp_base,
1426 struct dpp *dpp_base,
1430 struct dpp *dpp_base,
1436 struct dpp *dpp_base,
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Ddcn10_hw_sequencer.c1750 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn10_set_input_transfer_func() local
1754 if (dpp_base == NULL) in dcn10_set_input_transfer_func()
1761 !dpp_base->ctx->dc->debug.always_use_regamma in dcn10_set_input_transfer_func()
1764 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction); in dcn10_set_input_transfer_func()
1767 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1771 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB); in dcn10_set_input_transfer_func()
1774 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC); in dcn10_set_input_transfer_func()
1777 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1780 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); in dcn10_set_input_transfer_func()
1781 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); in dcn10_set_input_transfer_func()
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/inc/hw/
Ddpp.h162 struct dpp *dpp_base, const struct pwl_params *params);
164 void (*dpp_set_pre_degam)(struct dpp *dpp_base,
167 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
171 struct dpp *dpp_base,
234 struct dpp *dpp_base,
238 struct dpp *dpp_base,
241 void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
245 struct dpp *dpp_base,
252 void (*dpp_full_bypass)(struct dpp *dpp_base);
255 struct dpp *dpp_base,
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_dpp.c45 struct dpp *dpp_base, in dpp201_cnv_setup() argument
52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup()
170 dpp1_program_input_csc(dpp_base, color_space, select, NULL); in dpp201_cnv_setup()
178 dpp2_power_on_obuf(dpp_base, true); in dpp201_cnv_setup()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_hwseq.c442 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mpc_shaper_3dlut() local
455 &dpp_base->shaper_params, true); in dcn32_set_mpc_shaper_3dlut()
456 shaper_lut = &dpp_base->shaper_params; in dcn32_set_mpc_shaper_3dlut()
478 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mcm_luts() local
490 &dpp_base->regamma_params, false); in dcn32_set_mcm_luts()
491 lut_params = &dpp_base->regamma_params; in dcn32_set_mcm_luts()
504 &dpp_base->shaper_params, true); in dcn32_set_mcm_luts()
505 lut_params = &dpp_base->shaper_params; in dcn32_set_mcm_luts()
526 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_input_transfer_func() local
541 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn32_set_input_transfer_func()
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