Searched refs:dpm_level_enable_mask (Results 1 – 13 of 13) sorted by relevance
2605 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()3266 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()3320 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()3784 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3787 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3794 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3797 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3804 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3807 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3904 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()[all …]
238 struct ci_dpm_level_enable_mask dpm_level_enable_mask; member
3038 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { in smu7_force_dpm_highest()3040 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; in smu7_force_dpm_highest()3052 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_force_dpm_highest()3054 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; in smu7_force_dpm_highest()3067 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { in smu7_force_dpm_highest()3069 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; in smu7_force_dpm_highest()3093 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) in smu7_upload_dpm_level_enable_mask()3096 data->dpm_level_enable_mask.sclk_dpm_enable_mask, in smu7_upload_dpm_level_enable_mask()3101 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) in smu7_upload_dpm_level_enable_mask()3104 data->dpm_level_enable_mask.mclk_dpm_enable_mask, in smu7_upload_dpm_level_enable_mask()[all …]
306 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; member
369 struct vega10_dpmlevel_enable_mask dpm_level_enable_mask; member
371 struct vega12_dpmlevel_enable_mask dpm_level_enable_mask; member
494 struct vega20_dpmlevel_enable_mask dpm_level_enable_mask; member
594 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in vegam_populate_smc_link_level()910 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in vegam_populate_all_graphic_levels()915 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1; in vegam_populate_all_graphic_levels()926 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in vegam_populate_all_graphic_levels()927 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()931 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in vegam_populate_all_graphic_levels()932 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()937 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()1068 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = in vegam_populate_all_memory_levels()1073 (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1; in vegam_populate_all_memory_levels()
840 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in polaris10_populate_smc_link_level()1099 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in polaris10_populate_all_graphic_levels()1104 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask & (1 << i)) >> i; in polaris10_populate_all_graphic_levels()1115 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in polaris10_populate_all_graphic_levels()1116 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1120 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in polaris10_populate_all_graphic_levels()1121 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1126 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1238 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = in polaris10_populate_all_memory_levels()1243 (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask & (1 << i)) >> i; in polaris10_populate_all_memory_levels()
849 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in fiji_populate_smc_link_level()1043 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in fiji_populate_all_graphic_levels()1055 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in fiji_populate_all_graphic_levels()1056 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1060 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in fiji_populate_all_graphic_levels()1061 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1066 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1258 data->dpm_level_enable_mask.mclk_dpm_enable_mask = in fiji_populate_all_memory_levels()
502 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()1017 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()1340 …data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table-… in ci_populate_all_memory_levels()2878 data->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_update_uvd_smc_table()2882 data->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_update_uvd_smc_table()2887 data->dpm_level_enable_mask.uvd_dpm_enable_mask, in ci_update_uvd_smc_table()2910 data->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_update_vce_smc_table()2914 data->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_update_vce_smc_table()2919 data->dpm_level_enable_mask.vce_dpm_enable_mask, in ci_update_vce_smc_table()
532 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in tonga_populate_smc_link_level()732 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in tonga_populate_all_graphic_levels()745 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) in tonga_populate_all_graphic_levels()748 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in tonga_populate_all_graphic_levels()749 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()754 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in tonga_populate_all_graphic_levels()755 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()761 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()1131 …data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table-… in tonga_populate_all_memory_levels()
789 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in iceland_populate_smc_link_level()1002 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in iceland_populate_all_graphic_levels()1005 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1010 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1016 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1383 …data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table-… in iceland_populate_all_memory_levels()