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Searched refs:dp_phy (Results 1 – 25 of 25) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c62 enum drm_dp_phy dp_phy) in intel_dp_lttpr_phy_caps() argument
64 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; in intel_dp_lttpr_phy_caps()
69 enum drm_dp_phy dp_phy) in intel_dp_read_lttpr_phy_caps() argument
71 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); in intel_dp_read_lttpr_phy_caps()
73 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { in intel_dp_read_lttpr_phy_caps()
74 lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n"); in intel_dp_read_lttpr_phy_caps()
78 lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n", in intel_dp_read_lttpr_phy_caps()
233 enum drm_dp_phy dp_phy) in intel_dp_lttpr_voltage_max() argument
235 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); in intel_dp_lttpr_voltage_max()
244 enum drm_dp_phy dp_phy) in intel_dp_lttpr_preemph_max() argument
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Dintel_dp_link_training.h18 enum drm_dp_phy dp_phy,
22 enum drm_dp_phy dp_phy,
26 enum drm_dp_phy dp_phy);
33 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
/linux-6.6.21/drivers/phy/mediatek/
Dphy-mtk-dp.c87 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_init() local
97 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, in mtk_dp_phy_init()
99 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3, in mtk_dp_phy_init()
101 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3, in mtk_dp_phy_init()
103 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3, in mtk_dp_phy_init()
111 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_configure() local
134 regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); in mtk_dp_phy_configure()
137 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1, in mtk_dp_phy_configure()
145 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_reset() local
147 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, in mtk_dp_phy_reset()
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/linux-6.6.21/include/drm/display/
Ddrm_dp.h1389 #define DP_LTTPR_BASE(dp_phy) \ argument
1391 ((dp_phy) - DP_PHY_LTTPR1))
1393 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ argument
1394 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1397 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ argument
1398 DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
1401 #define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \ argument
1402 DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
1408 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ argument
1409 DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
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Ddrm_dp_helper.h48 enum drm_dp_phy dp_phy, bool uhbr);
50 enum drm_dp_phy dp_phy, bool uhbr);
72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
497 enum drm_dp_phy dp_phy,
554 enum drm_dp_phy dp_phy,
/linux-6.6.21/Documentation/devicetree/bindings/clock/
Dqcom,sc7180-dispcc.yaml74 <&dp_phy 0>,
75 <&dp_phy 1>;
Dqcom,dispcc-sm6350.yaml74 <&dp_phy 0>,
75 <&dp_phy 1>;
Dqcom,sc7280-dispcc.yaml78 <&dp_phy 0>,
79 <&dp_phy 1>,
Dqcom,dispcc-sm6125.yaml87 <&dp_phy 0>,
88 <&dp_phy 1>,
Dqcom,sdm845-dispcc.yaml86 <&dp_phy 0>,
87 <&dp_phy 1>;
Dqcom,dispcc-sm8x50.yaml94 <&dp_phy 0>,
95 <&dp_phy 1>;
/linux-6.6.21/drivers/gpu/drm/display/
Ddrm_dp_helper.c285 enum drm_dp_phy dp_phy, bool uhbr, bool cr) in __read_delay() argument
291 if (dp_phy == DP_PHY_DPRX) { in __read_delay()
312 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); in __read_delay()
319 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); in __read_delay()
340 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_clock_recovery_delay() argument
342 return __read_delay(aux, dpcd, dp_phy, uhbr, true); in drm_dp_read_clock_recovery_delay()
347 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_channel_eq_delay() argument
349 return __read_delay(aux, dpcd, dp_phy, uhbr, false); in drm_dp_read_channel_eq_delay()
416 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy) in drm_dp_phy_name() argument
430 if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) || in drm_dp_phy_name()
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/linux-6.6.21/Documentation/devicetree/bindings/display/msm/
Ddp-controller.yaml202 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
204 phys = <&dp_phy>;
Dqcom,sc7180-mdss.yaml258 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
259 phys = <&dp_phy>;
Dqcom,sc7280-mdss.yaml376 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
377 phys = <&dp_phy>;
/linux-6.6.21/Documentation/devicetree/bindings/display/rockchip/
Drockchip,analogix-dp.yaml68 phys = <&dp_phy>;
/linux-6.6.21/Documentation/devicetree/bindings/display/bridge/
Dcdns,mhdp8546.yaml140 phys = <&dp_phy>;
/linux-6.6.21/Documentation/devicetree/bindings/display/exynos/
Dexynos_dp.txt84 phys = <&dp_phy>;
/linux-6.6.21/drivers/phy/qualcomm/
Dphy-qcom-qmp-combo.c1413 struct phy *dp_phy; member
3403 return qmp->dp_phy; in qmp_combo_phy_xlate()
3489 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); in qmp_combo_probe()
3490 if (IS_ERR(qmp->dp_phy)) { in qmp_combo_probe()
3491 ret = PTR_ERR(qmp->dp_phy); in qmp_combo_probe()
3496 phy_set_drvdata(qmp->dp_phy, qmp); in qmp_combo_probe()
/linux-6.6.21/arch/arm/boot/dts/samsung/
Dexynos5250.dtsi298 dp_phy: dp-phy { label
1123 phys = <&dp_phy>;
Dexynos5420.dtsi930 dp_phy: dp-phy { label
1210 phys = <&dp_phy>;
/linux-6.6.21/arch/arm64/boot/dts/qcom/
Dsc7180.dtsi2832 dp_phy: dp-phy@88ea200 { label
3310 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3311 phys = <&dp_phy>;
3368 <&dp_phy 0>,
3369 <&dp_phy 1>;
Dsdm845.dtsi4018 dp_phy: dp-phy@88ea200 { label
4574 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4575 phys = <&dp_phy>;
4913 <&dp_phy 0>,
4914 <&dp_phy 1>;
Dsc7280.dtsi3380 dp_phy: dp-phy@88ea200 { label
3802 <&dp_phy 0>,
3803 <&dp_phy 1>,
4139 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4140 phys = <&dp_phy>;
Dsm8250.dtsi3600 dp_phy: dp-phy@88ea200 { label
4573 <&dp_phy 0>,
4574 <&dp_phy 1>;