| /linux-6.6.21/drivers/clk/tegra/ |
| D | clk-divider.c | 21 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
38 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local
43 reg = readl_relaxed(divider->reg); in clk_frac_div_recalc_rate()
45 if ((divider->flags & TEGRA_DIVIDER_UART) && in clk_frac_div_recalc_rate()
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
51 mul = get_mul(divider); in clk_frac_div_recalc_rate()
64 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_round_rate() local
71 div = get_div(divider, rate, output_rate); in clk_frac_div_round_rate()
[all …]
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| /linux-6.6.21/drivers/clk/ti/ |
| D | divider.c | 32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
45 max_val = divider->max; in _setup_mask()
47 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) && in _setup_mask()
48 !(divider->flags & CLK_DIVIDER_POWER_OF_TWO)) in _setup_mask()
52 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _setup_mask()
57 divider->mask = (1 << fls(mask)) - 1; in _setup_mask()
60 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) in _get_div() argument
62 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_div()
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| D | clk-dra7-atl.c | 49 u32 divider; /* Cached divider value */ member
85 cdesc->divider - 1); in atl_clk_enable()
120 return parent_rate / cdesc->divider; in atl_clk_recalc_rate()
126 unsigned divider; in atl_clk_round_rate() local
128 divider = (*parent_rate + rate / 2) / rate; in atl_clk_round_rate()
129 if (divider > DRA7_ATL_DIVIDER_MASK + 1) in atl_clk_round_rate()
130 divider = DRA7_ATL_DIVIDER_MASK + 1; in atl_clk_round_rate()
132 return *parent_rate / divider; in atl_clk_round_rate()
139 u32 divider; in atl_clk_set_rate() local
145 divider = ((parent_rate + rate / 2) / rate) - 1; in atl_clk_set_rate()
[all …]
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| /linux-6.6.21/drivers/clk/qcom/ |
| D | clk-regmap-divider.c | 21 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_ro_rate() local
22 struct clk_regmap *clkr = ÷r->clkr; in div_round_ro_rate()
25 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate()
26 val >>= divider->shift; in div_round_ro_rate()
27 val &= BIT(divider->width) - 1; in div_round_ro_rate()
29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate()
36 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local
38 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
45 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_set_rate() local
46 struct clk_regmap *clkr = ÷r->clkr; in div_set_rate()
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| /linux-6.6.21/drivers/clk/mvebu/ |
| D | dove-divider.c | 53 unsigned int divider; in dove_get_divider() local
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
64 return divider; in dove_get_divider()
70 unsigned int divider, max; in dove_calc_divider() local
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
79 divider = i; in dove_calc_divider()
88 if (set && (divider == 0 || divider >= max)) in dove_calc_divider()
90 if (divider >= max) in dove_calc_divider()
[all …]
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| /linux-6.6.21/drivers/clk/ |
| D | clk-divider.c | 29 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
31 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
32 return ioread32be(divider->reg); in clk_div_readl()
34 return readl(divider->reg); in clk_div_readl()
37 static inline void clk_div_writel(struct clk_divider *divider, u32 val) in clk_div_writel() argument
39 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_writel()
40 iowrite32be(val, divider->reg); in clk_div_writel()
42 writel(val, divider->reg); in clk_div_writel()
152 struct clk_divider *divider = to_clk_divider(hw); in clk_divider_recalc_rate() local
155 val = clk_div_readl(divider) >> divider->shift; in clk_divider_recalc_rate()
[all …]
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| D | clk-milbeaut.c | 379 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_recalc_rate() local
382 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_recalc_rate()
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()
385 return divider_recalc_rate(hw, parent_rate, val, divider->table, in m10v_clk_divider_recalc_rate()
386 divider->flags, divider->width); in m10v_clk_divider_recalc_rate()
392 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_round_rate() local
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in m10v_clk_divider_round_rate()
398 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_round_rate()
399 val &= clk_div_mask(divider->width); in m10v_clk_divider_round_rate()
401 return divider_ro_round_rate(hw, rate, prate, divider->table, in m10v_clk_divider_round_rate()
[all …]
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| /linux-6.6.21/drivers/clk/xilinx/ |
| D | clk-xlnx-clock-wizard.c | 153 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); in clk_wzrd_recalc_rate() local
154 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_recalc_rate()
157 val = readl(div_addr) >> divider->shift; in clk_wzrd_recalc_rate()
158 val &= div_mask(divider->width); in clk_wzrd_recalc_rate()
160 return divider_recalc_rate(hw, parent_rate, val, divider->table, in clk_wzrd_recalc_rate()
161 divider->flags, divider->width); in clk_wzrd_recalc_rate()
170 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); in clk_wzrd_dynamic_reconfig() local
171 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_dynamic_reconfig()
173 if (divider->lock) in clk_wzrd_dynamic_reconfig()
174 spin_lock_irqsave(divider->lock, flags); in clk_wzrd_dynamic_reconfig()
[all …]
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| /linux-6.6.21/drivers/clk/rockchip/ |
| D | clk-half-divider.c | 25 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local
28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
98 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_round_rate() local
102 divider->width, in clk_half_divider_round_rate()
103 divider->flags); in clk_half_divider_round_rate()
111 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_set_rate() local
118 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
120 if (divider->lock) in clk_half_divider_set_rate()
121 spin_lock_irqsave(divider->lock, flags); in clk_half_divider_set_rate()
[all …]
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| /linux-6.6.21/drivers/clk/imx/ |
| D | clk-composite-8m.c | 31 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_recalc_rate() local
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
95 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_set_rate() local
107 spin_lock_irqsave(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
109 orig = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
[all …]
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| D | clk-fixup-div.c | 24 struct clk_divider divider; member
31 struct clk_divider *divider = to_clk_divider(hw); in to_clk_fixup_div() local
33 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
41 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate()
49 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); in clk_fixup_div_round_rate()
57 unsigned int divider, value; in clk_fixup_div_set_rate() local
61 divider = parent_rate / rate; in clk_fixup_div_set_rate()
64 value = divider - 1; in clk_fixup_div_set_rate()
110 fixup_div->divider.reg = reg; in imx_clk_hw_fixup_divider()
111 fixup_div->divider.shift = shift; in imx_clk_hw_fixup_divider()
[all …]
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| D | clk-composite-93.c | 109 struct clk_divider *divider = to_clk_divider(hw); in imx93_clk_composite_divider_set_rate() local
115 value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags); in imx93_clk_composite_divider_set_rate()
119 if (divider->lock) in imx93_clk_composite_divider_set_rate()
120 spin_lock_irqsave(divider->lock, flags); in imx93_clk_composite_divider_set_rate()
122 val = readl(divider->reg); in imx93_clk_composite_divider_set_rate()
123 val &= ~(clk_div_mask(divider->width) << divider->shift); in imx93_clk_composite_divider_set_rate()
124 val |= (u32)value << divider->shift; in imx93_clk_composite_divider_set_rate()
125 writel(val, divider->reg); in imx93_clk_composite_divider_set_rate()
127 ret = imx93_clk_composite_wait_ready(hw, divider->reg); in imx93_clk_composite_divider_set_rate()
129 if (divider->lock) in imx93_clk_composite_divider_set_rate()
[all …]
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| D | clk-divider-gate.c | 15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
201 div_gate->divider.reg = reg; in imx_clk_hw_divider_gate()
202 div_gate->divider.shift = shift; in imx_clk_hw_divider_gate()
203 div_gate->divider.width = width; in imx_clk_hw_divider_gate()
204 div_gate->divider.lock = lock; in imx_clk_hw_divider_gate()
205 div_gate->divider.table = table; in imx_clk_hw_divider_gate()
206 div_gate->divider.hw.init = &init; in imx_clk_hw_divider_gate()
207 div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags; in imx_clk_hw_divider_gate()
213 hw = &div_gate->divider.hw; in imx_clk_hw_divider_gate()
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| /linux-6.6.21/drivers/clk/mxs/ |
| D | clk-div.c | 22 struct clk_divider divider; member
30 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
90 div->divider.reg = reg; in mxs_clk_div()
91 div->divider.shift = shift; in mxs_clk_div()
92 div->divider.width = width; in mxs_clk_div()
93 div->divider.flags = CLK_DIVIDER_ONE_BASED; in mxs_clk_div()
[all …]
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| /linux-6.6.21/drivers/clk/stm32/ |
| D | clk-stm32-core.c | 210 const struct stm32_div_cfg *divider = &data->dividers[div_id]; in stm32_divider_get_rate() local
214 val = readl(base + divider->offset) >> divider->shift; in stm32_divider_get_rate()
215 val &= clk_div_mask(divider->width); in stm32_divider_get_rate()
216 div = _get_div(divider->table, val, divider->flags, divider->width); in stm32_divider_get_rate()
219 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), in stm32_divider_get_rate()
233 const struct stm32_div_cfg *divider = &data->dividers[div_id]; in stm32_divider_set_rate() local
237 value = divider_get_val(rate, parent_rate, divider->table, in stm32_divider_set_rate()
238 divider->width, divider->flags); in stm32_divider_set_rate()
242 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { in stm32_divider_set_rate()
243 val = clk_div_mask(divider->width) << (divider->shift + 16); in stm32_divider_set_rate()
[all …]
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| /linux-6.6.21/drivers/clk/zynqmp/ |
| D | divider.c | 82 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_recalc_rate() local
84 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
85 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
100 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_recalc_rate()
104 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), in zynqmp_clk_divider_recalc_rate()
125 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_round_rate() local
127 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_round_rate()
128 u32 div_type = divider->div_type; in zynqmp_clk_divider_round_rate()
134 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in zynqmp_clk_divider_round_rate()
145 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_round_rate()
[all …]
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| /linux-6.6.21/drivers/clk/baikal-t1/ |
| D | ccu-div.c | 78 unsigned long divider) in ccu_div_var_update_clkdiv() argument
85 nd = ccu_div_lock_delay_ns(parent_rate, divider); in ccu_div_var_update_clkdiv()
211 unsigned long divider; in ccu_div_var_recalc_rate() local
215 divider = ccu_div_get(div->mask, val); in ccu_div_var_recalc_rate()
217 return ccu_div_calc_freq(parent_rate, divider); in ccu_div_var_recalc_rate()
224 unsigned long divider; in ccu_div_var_calc_divider() local
226 divider = parent_rate / rate; in ccu_div_var_calc_divider()
227 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN, in ccu_div_var_calc_divider()
235 unsigned long divider; in ccu_div_var_round_rate() local
237 divider = ccu_div_var_calc_divider(rate, *parent_rate, div->mask); in ccu_div_var_round_rate()
[all …]
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| /linux-6.6.21/drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 626 u32 divider; in vlv_set_cdclk() local
628 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
634 val |= divider; in vlv_set_cdclk()
638 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), in vlv_set_cdclk()
1229 u8 divider; /* CD2X divider * 2 */ member
1234 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1235 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1236 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1237 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1238 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
[all …]
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| /linux-6.6.21/Documentation/devicetree/bindings/iio/afe/ |
| D | voltage-divider.yaml | 4 $id: http://devicetree.org/schemas/iio/afe/voltage-divider.yaml#
7 title: Voltage divider
13 When an io-channel measures the midpoint of a voltage divider, the
15 of the divider. This binding describes the voltage divider in such
35 const: voltage-divider
48 Resistance R + Rout for the full divider. The io-channel is scaled by
64 * voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
79 compatible = "voltage-divider";
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| /linux-6.6.21/drivers/clk/davinci/ |
| D | pll.c | 244 struct clk_divider *divider; in davinci_pll_div_register() local
255 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in davinci_pll_div_register()
256 if (!divider) { in davinci_pll_div_register()
261 divider->reg = reg; in davinci_pll_div_register()
262 divider->shift = DIV_RATIO_SHIFT; in davinci_pll_div_register()
263 divider->width = DIV_RATIO_WIDTH; in davinci_pll_div_register()
266 divider->flags |= CLK_DIVIDER_READ_ONLY; in davinci_pll_div_register()
271 NULL, NULL, ÷r->hw, divider_ops, in davinci_pll_div_register()
281 kfree(divider); in davinci_pll_div_register()
579 struct clk_divider *divider; in davinci_pll_obsclk_register() local
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| /linux-6.6.21/Documentation/devicetree/bindings/clock/ti/ |
| D | divider.txt | 1 Binding for TI divider clock
6 register-mapped adjustable clock rate divider that does not gate and has
44 The binding must also provide the register to control the divider and
45 unless the divider array is provided, min and max dividers. Optionally
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
59 - reg : offset for register controlling adjustable divider
64 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
78 - ti,latch-bit : latch the divider value to HW, only needed if the register
79 access requires this. As an example dra76x DPLL_GMAC H14 divider implements
85 compatible = "ti,divider-clock";
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| /linux-6.6.21/Documentation/devicetree/bindings/clock/ |
| D | xgene.txt | 37 reset and/or the divider. Either may be omitted, but at least
55 - divider-offset : Offset to the divider CSR register from the divider base.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
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| D | keystone-pll.txt | 4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
29 reg-names = "control", "multiplier", "post-divider";
66 - compatible : shall be "ti,keystone,pll-divider-clock"
70 - bit-mask : arbitrary bitmask for programming the divider
78 compatible = "ti,keystone,pll-divider-clock";
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| /linux-6.6.21/drivers/i2c/busses/ |
| D | i2c-bcm2835.c | 93 u32 divider = DIV_ROUND_UP(parent_rate, rate); in clk_bcm2835_i2c_calc_divider() local
100 if (divider & 1) in clk_bcm2835_i2c_calc_divider()
101 divider++; in clk_bcm2835_i2c_calc_divider()
102 if ((divider < BCM2835_I2C_CDIV_MIN) || in clk_bcm2835_i2c_calc_divider()
103 (divider > BCM2835_I2C_CDIV_MAX)) in clk_bcm2835_i2c_calc_divider()
106 return divider; in clk_bcm2835_i2c_calc_divider()
114 u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate); in clk_bcm2835_i2c_set_rate() local
116 if (divider == -EINVAL) in clk_bcm2835_i2c_set_rate()
119 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider); in clk_bcm2835_i2c_set_rate()
126 fedl = max(divider / 16, 1u); in clk_bcm2835_i2c_set_rate()
[all …]
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| /linux-6.6.21/drivers/clk/x86/ |
| D | clk-cgu.c | 125 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); in lgm_clk_divider_recalc_rate() local
128 val = lgm_get_clk_val(divider->membase, divider->reg, in lgm_clk_divider_recalc_rate()
129 divider->shift, divider->width); in lgm_clk_divider_recalc_rate()
131 return divider_recalc_rate(hw, parent_rate, val, divider->table, in lgm_clk_divider_recalc_rate()
132 divider->flags, divider->width); in lgm_clk_divider_recalc_rate()
139 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); in lgm_clk_divider_round_rate() local
141 return divider_round_rate(hw, rate, prate, divider->table, in lgm_clk_divider_round_rate()
142 divider->width, divider->flags); in lgm_clk_divider_round_rate()
149 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); in lgm_clk_divider_set_rate() local
152 value = divider_get_val(rate, prate, divider->table, in lgm_clk_divider_set_rate()
[all …]
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