Searched refs:div_base (Results 1 – 5 of 5) sorted by relevance
| /linux-6.6.21/drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 27 void __iomem *div_base; member
82 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_recalc_rate()
132 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_set_rate()
134 writel(val, asiu->div_base + clk->div.offset); in iproc_asiu_clk_set_rate()
146 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_set_rate()
162 writel(val, asiu->div_base + clk->div.offset); in iproc_asiu_clk_set_rate()
200 asiu->div_base = of_iomap(node, 0); in iproc_asiu_setup()
201 if (WARN_ON(!asiu->div_base)) in iproc_asiu_setup()
251 iounmap(asiu->div_base); in iproc_asiu_setup()
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| /linux-6.6.21/drivers/pwm/ |
| D | pwm-samsung.c | 142 bits = (fls(divisor) - 1) - pwm->variant.div_base; in pwm_samsung_set_divisor()
212 for (div = variant->div_base; div < 4; ++div) in pwm_samsung_calc_tin()
220 div = variant->div_base; in pwm_samsung_calc_tin()
484 .div_base = 1,
491 .div_base = 0,
498 .div_base = 0,
505 .div_base = 0,
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| /linux-6.6.21/drivers/clocksource/ |
| D | samsung_pwm_timer.c | 107 bits = (fls(divisor) - 1) - pwm.variant.div_base; in samsung_timer_set_divisor()
469 .div_base = 1,
482 .div_base = 0,
495 .div_base = 0,
508 .div_base = 0,
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| /linux-6.6.21/include/clocksource/ |
| D | samsung_pwm.h | 23 u8 div_base; member
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| /linux-6.6.21/arch/arm/mach-s3c/ |
| D | s3c64xx.c | 163 .div_base = 0,
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