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Searched refs:disp_int (Results 1 – 10 of 10) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/radeon/
Drs600.c727 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); in rs600_irq_ack()
728 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
732 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
736 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
741 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
747 rdev->irq.stat_regs.r500.disp_int = 0; in rs600_irq_ack()
787 !rdev->irq.stat_regs.r500.disp_int && in rs600_irq_process()
792 rdev->irq.stat_regs.r500.disp_int || in rs600_irq_process()
799 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
808 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
[all …]
Dr600.c3917 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3928 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3941 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) in r600_irq_ack()
3943 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) in r600_irq_ack()
3945 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) in r600_irq_ack()
3947 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) in r600_irq_ack()
3949 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_ack()
3960 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_ack()
4135 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) in r600_irq_process()
4145 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in r600_irq_process()
[all …]
Devergreen.c4618 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in evergreen_irq_ack() local
4622 disp_int[i] = RREG32(evergreen_disp_int_status[i]); in evergreen_irq_ack()
4637 if (disp_int[j] & LB_D1_VBLANK_INTERRUPT) in evergreen_irq_ack()
4640 if (disp_int[j] & LB_D1_VLINE_INTERRUPT) in evergreen_irq_ack()
4647 if (disp_int[i] & DC_HPD1_INTERRUPT) in evergreen_irq_ack()
4652 if (disp_int[i] & DC_HPD1_RX_INTERRUPT) in evergreen_irq_ack()
4705 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in evergreen_irq_process() local
4777 if (!(disp_int[crtc_idx] & mask)) { in evergreen_irq_process()
4782 disp_int[crtc_idx] &= ~mask; in evergreen_irq_process()
4815 if (!(disp_int[hpd_idx] & mask)) in evergreen_irq_process()
[all …]
Dsi.c6147 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in si_irq_ack() local
6154 disp_int[i] = RREG32(si_disp_int_status[i]); in si_irq_ack()
6168 if (disp_int[j] & LB_D1_VBLANK_INTERRUPT) in si_irq_ack()
6171 if (disp_int[j] & LB_D1_VLINE_INTERRUPT) in si_irq_ack()
6178 if (disp_int[i] & DC_HPD1_INTERRUPT) in si_irq_ack()
6183 if (disp_int[i] & DC_HPD1_RX_INTERRUPT) in si_irq_ack()
6246 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in si_irq_process() local
6317 if (!(disp_int[crtc_idx] & mask)) { in si_irq_process()
6322 disp_int[crtc_idx] &= ~mask; in si_irq_process()
6355 if (!(disp_int[hpd_idx] & mask)) in si_irq_process()
[all …]
Dcik.c7289 rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS); in cik_irq_ack()
7320 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) in cik_irq_ack()
7322 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) in cik_irq_ack()
7363 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) { in cik_irq_ack()
7393 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) { in cik_irq_ack()
7584 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)) in cik_irq_process()
7594 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in cik_irq_process()
7599 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)) in cik_irq_process()
7602 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT; in cik_irq_process()
7774 if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT)) in cik_irq_process()
[all …]
Dradeon.h709 u32 disp_int; member
714 u32 disp_int; member
724 u32 disp_int[6]; member
730 u32 disp_int; member
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c2979 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v6_0_crtc_irq() local
2985 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v6_0_crtc_irq()
2996 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v6_0_crtc_irq()
3091 uint32_t disp_int, mask, tmp; in dce_v6_0_hpd_irq() local
3100 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()
3103 if (disp_int & mask) { in dce_v6_0_hpd_irq()
Ddce_v8_0.c3067 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v8_0_crtc_irq() local
3073 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v8_0_crtc_irq()
3084 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v8_0_crtc_irq()
3179 uint32_t disp_int, mask, tmp; in dce_v8_0_hpd_irq() local
3188 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v8_0_hpd_irq()
3191 if (disp_int & mask) { in dce_v8_0_hpd_irq()
Ddce_v10_0.c3247 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq() local
3252 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()
3264 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()
3284 uint32_t disp_int, mask; in dce_v10_0_hpd_irq() local
3293 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()
3296 if (disp_int & mask) { in dce_v10_0_hpd_irq()
Ddce_v11_0.c3378 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v11_0_crtc_irq() local
3384 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v11_0_crtc_irq()
3396 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v11_0_crtc_irq()
3416 uint32_t disp_int, mask; in dce_v11_0_hpd_irq() local
3425 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()
3428 if (disp_int & mask) { in dce_v11_0_hpd_irq()