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/linux-6.6.21/Documentation/devicetree/bindings/memory-controllers/
Dbrcm,brcmstb-memc-ddr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
16 - brcm,brcmstb-memc-ddr-rev-b.1.x
17 - brcm,brcmstb-memc-ddr-rev-b.2.0
18 - brcm,brcmstb-memc-ddr-rev-b.2.1
19 - brcm,brcmstb-memc-ddr-rev-b.2.2
20 - brcm,brcmstb-memc-ddr-rev-b.2.3
21 - brcm,brcmstb-memc-ddr-rev-b.2.5
22 - brcm,brcmstb-memc-ddr-rev-b.2.6
23 - brcm,brcmstb-memc-ddr-rev-b.2.7
24 - brcm,brcmstb-memc-ddr-rev-b.2.8
[all …]
Dqca,ath79-ddr-controller.yaml4 $id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
22 - const: qca,ar9132-ddr-controller
23 - const: qca,ar7240-ddr-controller
26 - qca,ar7100-ddr-controller
27 - qca,ar7240-ddr-controller
29 "#qca,ddr-wb-channel-cells":
41 - "#qca,ddr-wb-channel-cells"
49 compatible = "qca,ar9132-ddr-controller",
50 "qca,ar7240-ddr-controller";
53 #qca,ddr-wb-channel-cells = <1>;
[all …]
Dcalxeda-ddr-ctrlr.yaml4 $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
20 - calxeda,hb-ddr-ctrl
21 - calxeda,ecx-2000-ddr-ctrl
39 compatible = "calxeda,hb-ddr-ctrl";
/linux-6.6.21/Documentation/devicetree/bindings/perf/
Dfsl-imx-ddr.yaml4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
19 - fsl,imx8mm-ddr-pmu
20 - fsl,imx8mn-ddr-pmu
21 - fsl,imx8mp-ddr-pmu
22 - fsl,imx93-ddr-pmu
25 - fsl,imx8mm-ddr-pmu
26 - fsl,imx8mn-ddr-pmu
[all …]
Damlogic,g12-ddr-pmu.yaml4 $id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
21 - amlogic,g12a-ddr-pmu
22 - amlogic,g12b-ddr-pmu
23 - amlogic,sm1-ddr-pmu
49 compatible = "amlogic,g12a-ddr-pmu";
Dmarvell-cn10k-ddr.yaml4 $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
16 - marvell,cn10k-ddr-pmu
34 compatible = "marvell,cn10k-ddr-pmu";
/linux-6.6.21/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,brcmstb.txt169 "brcm,brcmstb-ddr-phy-v71.1"
170 "brcm,brcmstb-ddr-phy-v72.0"
171 "brcm,brcmstb-ddr-phy-v225.1"
172 "brcm,brcmstb-ddr-phy-v240.1"
173 "brcm,brcmstb-ddr-phy-v240.2"
182 - compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
190 See Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml for a
203 ddr-phy@f1106000 {
204 compatible = "brcm,brcmstb-ddr-phy-v240.1";
209 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
[all …]
/linux-6.6.21/Documentation/devicetree/bindings/interrupt-controller/
Dqca,ath79-cpu-intc.txt5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
34 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
35 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
43 #qca,ddr-wb-channel-cells = <1>;
/linux-6.6.21/Documentation/devicetree/bindings/mips/brcm/
Dsoc.txt75 memc-ddr@2000 {
79 ddr-phy@6000 {
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
99 ddr-phy@6000 {
100 compatible = "brcm,brcmstb-ddr-phy-v64.5";
110 "brcm,bcm7425-memc-ddr"
111 "brcm,bcm7429-memc-ddr"
112 "brcm,bcm7435-memc-ddr" and
113 "brcm,brcmstb-memc-ddr"
[all …]
/linux-6.6.21/arch/arm/boot/dts/broadcom/
Dbcm7445.dtsi239 memc-ddr@2000 {
240 compatible = "brcm,brcmstb-memc-ddr";
244 ddr-phy@6000 {
245 compatible = "brcm,brcmstb-ddr-phy-v240.1";
250 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
261 memc-ddr@2000 {
262 compatible = "brcm,brcmstb-memc-ddr";
266 ddr-phy@6000 {
267 compatible = "brcm,brcmstb-ddr-phy-v240.1";
272 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
[all …]
/linux-6.6.21/arch/mips/rb532/
Dprom.c103 struct ddr_ram __iomem *ddr; in prom_init() local
107 ddr = ioremap(ddr_reg[0].start, in prom_init()
110 if (!ddr) { in prom_init()
115 ddrbase = (phys_addr_t)&ddr->ddrbase; in prom_init()
116 memsize = (phys_addr_t)&ddr->ddrmask; in prom_init()
/linux-6.6.21/include/memory/
Drenesas-rpc-if.h26 bool ddr; member
32 bool ddr; member
44 bool ddr; member
52 bool ddr; member
/linux-6.6.21/Documentation/devicetree/bindings/clock/
Damlogic,meson8-ddr-clkc.yaml4 $id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
15 - amlogic,meson8-ddr-clkc
16 - amlogic,meson8b-ddr-clkc
43 compatible = "amlogic,meson8-ddr-clkc";
/linux-6.6.21/arch/mips/boot/dts/qca/
Dar9132.dtsi28 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
52 compatible = "qca,ar9132-ddr-controller",
53 "qca,ar7240-ddr-controller";
56 #qca,ddr-wb-channel-cells = <1>;
98 clock-output-names = "cpu", "ddr", "ahb";
/linux-6.6.21/drivers/media/pci/cx18/
Dcx18-cards.c74 .ddr = {
121 .ddr = {
168 .ddr = {
221 .ddr = {
274 .ddr = {
334 .ddr = {
390 .ddr = {
439 .ddr = {
487 .ddr = {
540 .ddr = {
Dcx18-firmware.c324 cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG); in cx18_init_memory()
328 cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH); in cx18_init_memory()
329 cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1); in cx18_init_memory()
330 cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2); in cx18_init_memory()
335 cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE); in cx18_init_memory()
336 cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS); in cx18_init_memory()
/linux-6.6.21/drivers/mtd/hyperbus/
Drpc-if.c29 .ddr = true,
33 .ddr = true,
38 .ddr = true,
42 .ddr = true,
/linux-6.6.21/sound/soc/intel/atom/sst/
Dsst_pci.c52 ctx->ddr = pcim_iomap(pci, 0, in sst_platform_get_resources()
54 if (!ctx->ddr) { in sst_platform_get_resources()
58 dev_dbg(ctx->dev, "sst: DDR Ptr %p\n", ctx->ddr); in sst_platform_get_resources()
60 ctx->ddr = NULL; in sst_platform_get_resources()
Dsst.c485 fw_save->ddr = kvzalloc(ctx->ddr_end - ctx->ddr_base, GFP_KERNEL); in intel_sst_suspend()
486 if (!fw_save->ddr) { in intel_sst_suspend()
488 goto ddr; in intel_sst_suspend()
494 memcpy32_fromio(fw_save->ddr, ctx->ddr, ctx->ddr_end - ctx->ddr_base); in intel_sst_suspend()
499 ddr: in intel_sst_suspend()
530 memcpy32_toio(ctx->ddr, fw_save->ddr, ctx->ddr_end - ctx->ddr_base); in intel_sst_resume()
535 kvfree(fw_save->ddr); in intel_sst_resume()
/linux-6.6.21/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr-channel.yaml4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
71 $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
80 $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
89 $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
98 $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml#
/linux-6.6.21/drivers/memory/
Drenesas-rpc-if.c191 u32 ddr; /* DRDRENR or SMDRENR */ member
426 rpc->ddr = 0; in rpcif_prepare()
433 if (op->cmd.ddr) in rpcif_prepare()
434 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5); in rpcif_prepare()
450 if (op->addr.ddr) in rpcif_prepare()
451 rpc->ddr |= RPCIF_SMDRENR_ADDRE; in rpcif_prepare()
468 if (op->option.ddr) in rpcif_prepare()
469 rpc->ddr |= RPCIF_SMDRENR_OPDRE; in rpcif_prepare()
488 if (op->data.ddr) in rpcif_prepare()
489 rpc->ddr |= RPCIF_SMDRENR_SPIDRE; in rpcif_prepare()
[all …]
/linux-6.6.21/Documentation/admin-guide/perf/
Dindex.rst13 imx-ddr
23 meson-ddr-pmu
/linux-6.6.21/arch/arm64/boot/dts/freescale/
Dimx8-ss-ddr.dtsi13 ddr_pmu0: ddr-pmu@5c020000 {
14 compatible = "fsl,imx8-ddr-pmu";
/linux-6.6.21/arch/arm/boot/dts/samsung/
Dexynos5260-xyref5260.dts97 mmc-ddr-1_8v;
100 samsung,dw-mshc-ddr-timing = <0 2>;
112 samsung,dw-mshc-ddr-timing = <1 2>;
/linux-6.6.21/arch/mips/boot/dts/brcm/
Dbcm7425.dtsi544 memc-ddr@2000 {
545 compatible = "brcm,brcmstb-memc-ddr";
549 ddr-phy@6000 {
550 compatible = "brcm,brcmstb-ddr-phy";
555 compatible = "brcm,brcmstb-ddr-shimphy";
571 memc-ddr@2000 {
572 compatible = "brcm,brcmstb-memc-ddr";
576 ddr-phy@6000 {
577 compatible = "brcm,brcmstb-ddr-phy";
582 compatible = "brcm,brcmstb-ddr-shimphy";

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