Searched refs:cx0pll_state (Results 1 – 4 of 4) sorted by relevance
1766 struct intel_cx0pll_state *pll_state = &crtc_state->cx0pll_state; in intel_c10pll_update_pll()1798 crtc_state->cx0pll_state.c10 = *tables[i]; in intel_c10pll_calc_state()1840 const struct intel_c10pll_state *pll_state = &crtc_state->cx0pll_state.c10; in intel_c10_pll_program()2023 &crtc_state->cx0pll_state.c20) == 0) in intel_c20pll_calc_state()2033 crtc_state->cx0pll_state.c20 = *tables[i]; in intel_c20pll_calc_state()2240 const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20; in intel_c20_pll_program()2432 val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; in intel_program_port_clock_ctl()2434 val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; in intel_program_port_clock_ctl()3003 struct intel_c10pll_state *mpllb_sw_state = &new_crtc_state->cx0pll_state.c10; in intel_c10pll_state_verify()
3859 intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10); in mtl_ddi_get_config()3860 intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10); in mtl_ddi_get_config()3861 crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10); in mtl_ddi_get_config()3863 intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20); in mtl_ddi_get_config()3864 intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20); in mtl_ddi_get_config()3865 crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20); in mtl_ddi_get_config()
1016 crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10); in mtl_crtc_compute_clock()1018 crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20); in mtl_crtc_compute_clock()
1175 struct intel_cx0pll_state cx0pll_state; member