| /linux-6.6.21/arch/mips/include/asm/octeon/ |
| D | cvmx.h | 266 static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) in cvmx_write_csr() argument
268 cvmx_write64(csr_addr, val); in cvmx_write_csr()
276 if (((csr_addr >> 40) & 0x7ffff) == (0x118)) in cvmx_write_csr()
280 static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val) in cvmx_writeq_csr() argument
282 cvmx_write_csr((__force uint64_t)csr_addr, val); in cvmx_writeq_csr()
291 static inline uint64_t cvmx_read_csr(uint64_t csr_addr) in cvmx_read_csr() argument
293 uint64_t val = cvmx_read64(csr_addr); in cvmx_read_csr()
297 static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr) in cvmx_readq_csr() argument
299 return cvmx_read_csr((__force uint64_t) csr_addr); in cvmx_readq_csr()
308 static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr) in cvmx_read_csr_async() argument
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| D | octeon-model.h | 314 static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
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| /linux-6.6.21/drivers/crypto/intel/qat/qat_common/ |
| D | adf_transport.c | 66 csr_ops->write_csr_int_col_en(bank->csr_addr, bank->bank_number, in adf_enable_ring_irq()
68 csr_ops->write_csr_int_col_ctl(bank->csr_addr, bank->bank_number, in adf_enable_ring_irq()
79 csr_ops->write_csr_int_col_en(bank->csr_addr, bank->bank_number, in adf_disable_ring_irq()
104 csr_ops->write_csr_ring_tail(ring->bank->csr_addr, in adf_send_message()
129 csr_ops->write_csr_ring_head(ring->bank->csr_addr, in adf_handle_response()
141 csr_ops->write_csr_ring_config(ring->bank->csr_addr, in adf_configure_tx_ring()
155 csr_ops->write_csr_ring_config(ring->bank->csr_addr, in adf_configure_rx_ring()
196 csr_ops->write_csr_ring_base(ring->bank->csr_addr, in adf_init_ring()
314 csr_ops->write_csr_ring_config(bank->csr_addr, bank->bank_number, in adf_remove_ring()
316 csr_ops->write_csr_ring_base(bank->csr_addr, bank->bank_number, in adf_remove_ring()
[all …]
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| D | adf_hw_arbiter.c | 10 #define WRITE_CSR_ARB_SARCONFIG(csr_addr, arb_offset, index, value) \ argument
11 ADF_CSR_WR(csr_addr, (arb_offset) + \
14 #define WRITE_CSR_ARB_WT2SAM(csr_addr, arb_offset, wt_offset, index, value) \ argument
15 ADF_CSR_WR(csr_addr, ((arb_offset) + (wt_offset)) + \
21 void __iomem *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb()
69 csr_ops->write_csr_ring_srv_arb_en(ring->bank->csr_addr, in adf_update_ring_arb()
89 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb()
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| D | adf_gen2_hw_data.h | 112 #define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \ argument
113 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
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| D | adf_transport_debug.c | 46 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show()
156 void __iomem *csr = bank->csr_addr; in adf_bank_show()
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| D | adf_transport_internal.h | 34 void __iomem *csr_addr; member
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| D | adf_vf_isr.c | 169 csr_ops->write_csr_int_flag_and_col(bank->csr_addr, in adf_isr()
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| D | qat_hal.c | 444 void __iomem *csr_addr = in qat_hal_init_esram() local
453 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
457 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
459 ADF_CSR_WR(csr_addr, 0, csr_val); in qat_hal_init_esram()
463 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
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| D | adf_isr.c | 52 csr_ops->write_csr_int_flag_and_col(bank->csr_addr, bank->bank_number, in adf_msix_isr_bundle()
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| /linux-6.6.21/drivers/net/ethernet/huawei/hinic/ |
| D | hinic_hw_dev.h | 543 u32 csr_addr; member
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| D | hinic_devlink.c | 436 err = devlink_fmsg_u32_pair_put(fmsg, "csr_addr", event->event.phy_fault.csr_addr); in fault_report_show()
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| /linux-6.6.21/drivers/staging/octeon/ |
| D | octeon-stubs.h | 1233 static inline uint64_t cvmx_read_csr(uint64_t csr_addr) in cvmx_read_csr() argument
1238 static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) in cvmx_write_csr() argument
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