1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2018-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef HL_BOOT_IF_H 9 #define HL_BOOT_IF_H 10 11 #define LKD_HARD_RESET_MAGIC 0xED7BD694 /* deprecated - do not use */ 12 #define HL_POWER9_HOST_MAGIC 0x1DA30009 13 14 #define BOOT_FIT_SRAM_OFFSET 0x200000 15 16 #define VERSION_MAX_LEN 128 17 18 enum cpu_boot_err { 19 CPU_BOOT_ERR_DRAM_INIT_FAIL = 0, 20 CPU_BOOT_ERR_FIT_CORRUPTED = 1, 21 CPU_BOOT_ERR_TS_INIT_FAIL = 2, 22 CPU_BOOT_ERR_DRAM_SKIPPED = 3, 23 CPU_BOOT_ERR_BMC_WAIT_SKIPPED = 4, 24 CPU_BOOT_ERR_NIC_DATA_NOT_RDY = 5, 25 CPU_BOOT_ERR_NIC_FW_FAIL = 6, 26 CPU_BOOT_ERR_SECURITY_NOT_RDY = 7, 27 CPU_BOOT_ERR_SECURITY_FAIL = 8, 28 CPU_BOOT_ERR_EFUSE_FAIL = 9, 29 CPU_BOOT_ERR_PRI_IMG_VER_FAIL = 10, 30 CPU_BOOT_ERR_SEC_IMG_VER_FAIL = 11, 31 CPU_BOOT_ERR_PLL_FAIL = 12, 32 CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL = 13, 33 CPU_BOOT_ERR_BOOT_FW_CRIT_ERR = 18, 34 CPU_BOOT_ERR_BINNING_FAIL = 19, 35 CPU_BOOT_ERR_TPM_FAIL = 20, 36 CPU_BOOT_ERR_TMP_THRESH_INIT_FAIL = 21, 37 CPU_BOOT_ERR_EEPROM_FAIL = 22, 38 CPU_BOOT_ERR_ENG_ARC_MEM_SCRUB_FAIL = 23, 39 CPU_BOOT_ERR_ENABLED = 31, 40 CPU_BOOT_ERR_SCND_EN = 63, 41 CPU_BOOT_ERR_LAST = 64 /* we have 2 registers of 32 bits */ 42 }; 43 44 /* 45 * Mask for fatal failures 46 * This mask contains all possible fatal failures, and a dynamic code 47 * will clear the non-relevant ones. 48 */ 49 #define CPU_BOOT_ERR_FATAL_MASK \ 50 ((1 << CPU_BOOT_ERR_DRAM_INIT_FAIL) | \ 51 (1 << CPU_BOOT_ERR_PLL_FAIL) | \ 52 (1 << CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL) | \ 53 (1 << CPU_BOOT_ERR_BINNING_FAIL) | \ 54 (1 << CPU_BOOT_ERR_DRAM_SKIPPED) | \ 55 (1 << CPU_BOOT_ERR_ENG_ARC_MEM_SCRUB_FAIL) | \ 56 (1 << CPU_BOOT_ERR_EEPROM_FAIL)) 57 58 /* 59 * CPU error bits in BOOT_ERROR registers 60 * 61 * CPU_BOOT_ERR0_DRAM_INIT_FAIL DRAM initialization failed. 62 * DRAM is not reliable to use. 63 * 64 * CPU_BOOT_ERR0_FIT_CORRUPTED FIT data integrity verification of the 65 * image provided by the host has failed. 66 * 67 * CPU_BOOT_ERR0_TS_INIT_FAIL Thermal Sensor initialization failed. 68 * Boot continues as usual, but keep in 69 * mind this is a warning. 70 * 71 * CPU_BOOT_ERR0_DRAM_SKIPPED DRAM initialization has been skipped. 72 * Skipping DRAM initialization has been 73 * requested (e.g. strap, command, etc.) 74 * and FW skipped the DRAM initialization. 75 * Host can initialize the DRAM. 76 * 77 * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED Waiting for BMC data will be skipped. 78 * Meaning the BMC data might not be 79 * available until reset. 80 * 81 * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY NIC data from BMC is not ready. 82 * BMC has not provided the NIC data yet. 83 * Once provided this bit will be cleared. 84 * 85 * CPU_BOOT_ERR0_NIC_FW_FAIL NIC FW loading failed. 86 * The NIC FW loading and initialization 87 * failed. This means NICs are not usable. 88 * 89 * CPU_BOOT_ERR0_SECURITY_NOT_RDY Chip security initialization has been 90 * started, but is not ready yet - chip 91 * cannot be accessed. 92 * 93 * CPU_BOOT_ERR0_SECURITY_FAIL Security related tasks have failed. 94 * The tasks are security init (root of 95 * trust), boot authentication (chain of 96 * trust), data packets authentication. 97 * 98 * CPU_BOOT_ERR0_EFUSE_FAIL Reading from eFuse failed. 99 * The PCI device ID might be wrong. 100 * 101 * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL Verification of primary image failed. 102 * It mean that ppboot checksum 103 * verification for the preboot primary 104 * image has failed to match expected 105 * checksum. Trying to program image again 106 * might solve this. 107 * 108 * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL Verification of secondary image failed. 109 * It mean that ppboot checksum 110 * verification for the preboot secondary 111 * image has failed to match expected 112 * checksum. Trying to program image again 113 * might solve this. 114 * 115 * CPU_BOOT_ERR0_PLL_FAIL PLL settings failed, meaning that one 116 * of the PLLs remains in REF_CLK 117 * 118 * CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL Device is unusable and customer support 119 * should be contacted. 120 * 121 * CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR Critical error was detected during 122 * the execution of ppboot or preboot. 123 * for example: stack overflow. 124 * 125 * CPU_BOOT_ERR0_BINNING_FAIL Binning settings failed, meaning 126 * malfunctioning components might still be 127 * in use. 128 * 129 * CPU_BOOT_ERR0_TPM_FAIL TPM verification flow failed. 130 * 131 * CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL Failed to set threshold for tmperature 132 * sensor. 133 * 134 * CPU_BOOT_ERR_EEPROM_FAIL Failed reading EEPROM data. Defaults 135 * are used. 136 * 137 * CPU_BOOT_ERR_ENG_ARC_MEM_SCRUB_FAIL Failed scrubbing the Engines/ARCFarm 138 * memories. Boot disabled until reset. 139 * 140 * CPU_BOOT_ERR0_ENABLED Error registers enabled. 141 * This is a main indication that the 142 * running FW populates the error 143 * registers. Meaning the error bits are 144 * not garbage, but actual error statuses. 145 */ 146 #define CPU_BOOT_ERR0_DRAM_INIT_FAIL (1 << CPU_BOOT_ERR_DRAM_INIT_FAIL) 147 #define CPU_BOOT_ERR0_FIT_CORRUPTED (1 << CPU_BOOT_ERR_FIT_CORRUPTED) 148 #define CPU_BOOT_ERR0_TS_INIT_FAIL (1 << CPU_BOOT_ERR_TS_INIT_FAIL) 149 #define CPU_BOOT_ERR0_DRAM_SKIPPED (1 << CPU_BOOT_ERR_DRAM_SKIPPED) 150 #define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED (1 << CPU_BOOT_ERR_BMC_WAIT_SKIPPED) 151 #define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY (1 << CPU_BOOT_ERR_NIC_DATA_NOT_RDY) 152 #define CPU_BOOT_ERR0_NIC_FW_FAIL (1 << CPU_BOOT_ERR_NIC_FW_FAIL) 153 #define CPU_BOOT_ERR0_SECURITY_NOT_RDY (1 << CPU_BOOT_ERR_SECURITY_NOT_RDY) 154 #define CPU_BOOT_ERR0_SECURITY_FAIL (1 << CPU_BOOT_ERR_SECURITY_FAIL) 155 #define CPU_BOOT_ERR0_EFUSE_FAIL (1 << CPU_BOOT_ERR_EFUSE_FAIL) 156 #define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL (1 << CPU_BOOT_ERR_PRI_IMG_VER_FAIL) 157 #define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL (1 << CPU_BOOT_ERR_SEC_IMG_VER_FAIL) 158 #define CPU_BOOT_ERR0_PLL_FAIL (1 << CPU_BOOT_ERR_PLL_FAIL) 159 #define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL (1 << CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL) 160 #define CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR (1 << CPU_BOOT_ERR_BOOT_FW_CRIT_ERR) 161 #define CPU_BOOT_ERR0_BINNING_FAIL (1 << CPU_BOOT_ERR_BINNING_FAIL) 162 #define CPU_BOOT_ERR0_TPM_FAIL (1 << CPU_BOOT_ERR_TPM_FAIL) 163 #define CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL (1 << CPU_BOOT_ERR_TMP_THRESH_INIT_FAIL) 164 #define CPU_BOOT_ERR0_EEPROM_FAIL (1 << CPU_BOOT_ERR_EEPROM_FAIL) 165 #define CPU_BOOT_ERR0_ENG_ARC_MEM_SCRUB_FAIL (1 << CPU_BOOT_ERR_ENG_ARC_MEM_SCRUB_FAIL) 166 #define CPU_BOOT_ERR0_ENABLED (1 << CPU_BOOT_ERR_ENABLED) 167 #define CPU_BOOT_ERR1_ENABLED (1 << CPU_BOOT_ERR_ENABLED) 168 169 enum cpu_boot_dev_sts { 170 CPU_BOOT_DEV_STS_SECURITY_EN = 0, 171 CPU_BOOT_DEV_STS_DEBUG_EN = 1, 172 CPU_BOOT_DEV_STS_WATCHDOG_EN = 2, 173 CPU_BOOT_DEV_STS_DRAM_INIT_EN = 3, 174 CPU_BOOT_DEV_STS_BMC_WAIT_EN = 4, 175 CPU_BOOT_DEV_STS_E2E_CRED_EN = 5, 176 CPU_BOOT_DEV_STS_HBM_CRED_EN = 6, 177 CPU_BOOT_DEV_STS_RL_EN = 7, 178 CPU_BOOT_DEV_STS_SRAM_SCR_EN = 8, 179 CPU_BOOT_DEV_STS_DRAM_SCR_EN = 9, 180 CPU_BOOT_DEV_STS_FW_HARD_RST_EN = 10, 181 CPU_BOOT_DEV_STS_PLL_INFO_EN = 11, 182 CPU_BOOT_DEV_STS_SP_SRAM_EN = 12, 183 CPU_BOOT_DEV_STS_CLK_GATE_EN = 13, 184 CPU_BOOT_DEV_STS_HBM_ECC_EN = 14, 185 CPU_BOOT_DEV_STS_PKT_PI_ACK_EN = 15, 186 CPU_BOOT_DEV_STS_FW_LD_COM_EN = 16, 187 CPU_BOOT_DEV_STS_FW_IATU_CONF_EN = 17, 188 CPU_BOOT_DEV_STS_FW_NIC_MAC_EN = 18, 189 CPU_BOOT_DEV_STS_DYN_PLL_EN = 19, 190 CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN = 20, 191 CPU_BOOT_DEV_STS_EQ_INDEX_EN = 21, 192 CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN = 22, 193 CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN = 23, 194 CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN = 24, 195 CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN = 25, 196 CPU_BOOT_DEV_STS_MAP_HWMON_EN = 26, 197 CPU_BOOT_DEV_STS_ENABLED = 31, 198 CPU_BOOT_DEV_STS_SCND_EN = 63, 199 CPU_BOOT_DEV_STS_LAST = 64 /* we have 2 registers of 32 bits */ 200 }; 201 202 /* 203 * BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers 204 * 205 * CPU_BOOT_DEV_STS0_SECURITY_EN Security is Enabled. 206 * This is an indication for security 207 * enabled in FW, which means that 208 * all conditions for security are met: 209 * device is indicated as security enabled, 210 * registers are protected, and device 211 * uses keys for image verification. 212 * Initialized in: preboot 213 * 214 * CPU_BOOT_DEV_STS0_DEBUG_EN Debug is enabled. 215 * Enabled when JTAG or DEBUG is enabled 216 * in FW. 217 * Initialized in: preboot 218 * 219 * CPU_BOOT_DEV_STS0_WATCHDOG_EN Watchdog is enabled. 220 * Watchdog is enabled in FW. 221 * Initialized in: preboot 222 * 223 * CPU_BOOT_DEV_STS0_DRAM_INIT_EN DRAM initialization is enabled. 224 * DRAM initialization has been done in FW. 225 * Initialized in: u-boot 226 * 227 * CPU_BOOT_DEV_STS0_BMC_WAIT_EN Waiting for BMC data enabled. 228 * If set, it means that during boot, 229 * FW waited for BMC data. 230 * Initialized in: u-boot 231 * 232 * CPU_BOOT_DEV_STS0_E2E_CRED_EN E2E credits initialized. 233 * FW initialized E2E credits. 234 * Initialized in: u-boot 235 * 236 * CPU_BOOT_DEV_STS0_HBM_CRED_EN HBM credits initialized. 237 * FW initialized HBM credits. 238 * Initialized in: u-boot 239 * 240 * CPU_BOOT_DEV_STS0_RL_EN Rate limiter initialized. 241 * FW initialized rate limiter. 242 * Initialized in: u-boot 243 * 244 * CPU_BOOT_DEV_STS0_SRAM_SCR_EN SRAM scrambler enabled. 245 * FW initialized SRAM scrambler. 246 * Initialized in: linux 247 * 248 * CPU_BOOT_DEV_STS0_DRAM_SCR_EN DRAM scrambler enabled. 249 * FW initialized DRAM scrambler. 250 * Initialized in: u-boot 251 * 252 * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN FW hard reset procedure is enabled. 253 * FW has the hard reset procedure 254 * implemented. This means that FW will 255 * perform hard reset procedure on 256 * receiving the halt-machine event. 257 * Initialized in: preboot, u-boot, linux 258 * 259 * CPU_BOOT_DEV_STS0_PLL_INFO_EN FW retrieval of PLL info is enabled. 260 * Initialized in: linux 261 * 262 * CPU_BOOT_DEV_STS0_SP_SRAM_EN SP SRAM is initialized and available 263 * for use. 264 * Initialized in: preboot 265 * 266 * CPU_BOOT_DEV_STS0_CLK_GATE_EN Clock Gating enabled. 267 * FW initialized Clock Gating. 268 * Initialized in: preboot 269 * 270 * CPU_BOOT_DEV_STS0_HBM_ECC_EN HBM ECC handling Enabled. 271 * FW handles HBM ECC indications. 272 * Initialized in: linux 273 * 274 * CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN Packets ack value used in the armcpd 275 * is set to the PI counter. 276 * Initialized in: linux 277 * 278 * CPU_BOOT_DEV_STS0_FW_LD_COM_EN Flexible FW loading communication 279 * protocol is enabled. 280 * Initialized in: preboot 281 * 282 * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN FW iATU configuration is enabled. 283 * This bit if set, means the iATU has been 284 * configured and is ready for use. 285 * Initialized in: ppboot 286 * 287 * CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN NIC MAC channels init is done by FW and 288 * any access to them is done via the FW. 289 * Initialized in: linux 290 * 291 * CPU_BOOT_DEV_STS0_DYN_PLL_EN Dynamic PLL configuration is enabled. 292 * FW sends to host a bitmap of supported 293 * PLLs. 294 * Initialized in: linux 295 * 296 * CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN GIC access permission only from 297 * previleged entity. FW sets this status 298 * bit for host. If this bit is set then 299 * GIC can not be accessed from host. 300 * Initialized in: linux 301 * 302 * CPU_BOOT_DEV_STS0_EQ_INDEX_EN Event Queue (EQ) index is a running 303 * index for each new event sent to host. 304 * This is used as a method in host to 305 * identify that the waiting event in 306 * queue is actually a new event which 307 * was not served before. 308 * Initialized in: linux 309 * 310 * CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN Use multiple scratchpad interfaces to 311 * prevent IRQs overriding each other. 312 * Initialized in: linux 313 * 314 * CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN 315 * NIC STAT and XPCS91 access is restricted 316 * and is done via FW only. 317 * Initialized in: linux 318 * 319 * CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN 320 * NIC STAT get all is supported. 321 * Initialized in: linux 322 * 323 * CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN 324 * F/W checks if the device is idle by reading defined set 325 * of registers. It returns a bitmask of all the engines, 326 * where a bit is set if the engine is not idle. 327 * Initialized in: linux 328 * 329 * CPU_BOOT_DEV_STS0_MAP_HWMON_EN 330 * If set, means f/w supports proprietary 331 * HWMON enum mapping to cpucp enums. 332 * Initialized in: linux 333 * 334 * CPU_BOOT_DEV_STS0_ENABLED Device status register enabled. 335 * This is a main indication that the 336 * running FW populates the device status 337 * register. Meaning the device status 338 * bits are not garbage, but actual 339 * statuses. 340 * Initialized in: preboot 341 * 342 */ 343 #define CPU_BOOT_DEV_STS0_SECURITY_EN (1 << CPU_BOOT_DEV_STS_SECURITY_EN) 344 #define CPU_BOOT_DEV_STS0_DEBUG_EN (1 << CPU_BOOT_DEV_STS_DEBUG_EN) 345 #define CPU_BOOT_DEV_STS0_WATCHDOG_EN (1 << CPU_BOOT_DEV_STS_WATCHDOG_EN) 346 #define CPU_BOOT_DEV_STS0_DRAM_INIT_EN (1 << CPU_BOOT_DEV_STS_DRAM_INIT_EN) 347 #define CPU_BOOT_DEV_STS0_BMC_WAIT_EN (1 << CPU_BOOT_DEV_STS_BMC_WAIT_EN) 348 #define CPU_BOOT_DEV_STS0_E2E_CRED_EN (1 << CPU_BOOT_DEV_STS_E2E_CRED_EN) 349 #define CPU_BOOT_DEV_STS0_HBM_CRED_EN (1 << CPU_BOOT_DEV_STS_HBM_CRED_EN) 350 #define CPU_BOOT_DEV_STS0_RL_EN (1 << CPU_BOOT_DEV_STS_RL_EN) 351 #define CPU_BOOT_DEV_STS0_SRAM_SCR_EN (1 << CPU_BOOT_DEV_STS_SRAM_SCR_EN) 352 #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN (1 << CPU_BOOT_DEV_STS_DRAM_SCR_EN) 353 #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN (1 << CPU_BOOT_DEV_STS_FW_HARD_RST_EN) 354 #define CPU_BOOT_DEV_STS0_PLL_INFO_EN (1 << CPU_BOOT_DEV_STS_PLL_INFO_EN) 355 #define CPU_BOOT_DEV_STS0_SP_SRAM_EN (1 << CPU_BOOT_DEV_STS_SP_SRAM_EN) 356 #define CPU_BOOT_DEV_STS0_CLK_GATE_EN (1 << CPU_BOOT_DEV_STS_CLK_GATE_EN) 357 #define CPU_BOOT_DEV_STS0_HBM_ECC_EN (1 << CPU_BOOT_DEV_STS_HBM_ECC_EN) 358 #define CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN (1 << CPU_BOOT_DEV_STS_PKT_PI_ACK_EN) 359 #define CPU_BOOT_DEV_STS0_FW_LD_COM_EN (1 << CPU_BOOT_DEV_STS_FW_LD_COM_EN) 360 #define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN (1 << CPU_BOOT_DEV_STS_FW_IATU_CONF_EN) 361 #define CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_MAC_EN) 362 #define CPU_BOOT_DEV_STS0_DYN_PLL_EN (1 << CPU_BOOT_DEV_STS_DYN_PLL_EN) 363 #define CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN (1 << CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN) 364 #define CPU_BOOT_DEV_STS0_EQ_INDEX_EN (1 << CPU_BOOT_DEV_STS_EQ_INDEX_EN) 365 #define CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN (1 << CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN) 366 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN) 367 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN (1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN) 368 #define CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN (1 << CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN) 369 #define CPU_BOOT_DEV_STS0_MAP_HWMON_EN (1 << CPU_BOOT_DEV_STS_MAP_HWMON_EN) 370 #define CPU_BOOT_DEV_STS0_ENABLED (1 << CPU_BOOT_DEV_STS_ENABLED) 371 #define CPU_BOOT_DEV_STS1_ENABLED (1 << CPU_BOOT_DEV_STS_ENABLED) 372 373 enum cpu_boot_status { 374 CPU_BOOT_STATUS_NA = 0, /* Default value after reset of chip */ 375 CPU_BOOT_STATUS_IN_WFE = 1, 376 CPU_BOOT_STATUS_DRAM_RDY = 2, 377 CPU_BOOT_STATUS_SRAM_AVAIL = 3, 378 CPU_BOOT_STATUS_IN_BTL = 4, /* BTL is H/W FSM */ 379 CPU_BOOT_STATUS_IN_PREBOOT = 5, 380 CPU_BOOT_STATUS_IN_SPL, /* deprecated - not reported */ 381 CPU_BOOT_STATUS_IN_UBOOT = 7, 382 CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */ 383 CPU_BOOT_STATUS_FIT_CORRUPTED, /* deprecated - will be removed */ 384 /* U-Boot console prompt activated, commands are not processed */ 385 CPU_BOOT_STATUS_UBOOT_NOT_READY = 10, 386 /* Finished NICs init, reported after DRAM and NICs */ 387 CPU_BOOT_STATUS_NIC_FW_RDY = 11, 388 CPU_BOOT_STATUS_TS_INIT_FAIL, /* deprecated - will be removed */ 389 CPU_BOOT_STATUS_DRAM_SKIPPED, /* deprecated - will be removed */ 390 CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */ 391 /* Last boot loader progress status, ready to receive commands */ 392 CPU_BOOT_STATUS_READY_TO_BOOT = 15, 393 /* Internal Boot finished, ready for boot-fit */ 394 CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16, 395 /* Internal Security has been initialized, device can be accessed */ 396 CPU_BOOT_STATUS_SECURITY_READY = 17, 397 }; 398 399 enum kmd_msg { 400 KMD_MSG_NA = 0, 401 KMD_MSG_GOTO_WFE, 402 KMD_MSG_FIT_RDY, 403 KMD_MSG_SKIP_BMC, 404 RESERVED, 405 KMD_MSG_RST_DEV, 406 KMD_MSG_LAST 407 }; 408 409 enum cpu_msg_status { 410 CPU_MSG_CLR = 0, 411 CPU_MSG_OK, 412 CPU_MSG_ERR, 413 }; 414 415 /* communication registers mapping - consider ABI when changing */ 416 struct cpu_dyn_regs { 417 __le32 cpu_pq_base_addr_low; 418 __le32 cpu_pq_base_addr_high; 419 __le32 cpu_pq_length; 420 __le32 cpu_pq_init_status; 421 __le32 cpu_eq_base_addr_low; 422 __le32 cpu_eq_base_addr_high; 423 __le32 cpu_eq_length; 424 __le32 cpu_eq_ci; 425 __le32 cpu_cq_base_addr_low; 426 __le32 cpu_cq_base_addr_high; 427 __le32 cpu_cq_length; 428 __le32 cpu_pf_pq_pi; 429 __le32 cpu_boot_dev_sts0; 430 __le32 cpu_boot_dev_sts1; 431 __le32 cpu_boot_err0; 432 __le32 cpu_boot_err1; 433 __le32 cpu_boot_status; 434 __le32 fw_upd_sts; 435 __le32 fw_upd_cmd; 436 __le32 fw_upd_pending_sts; 437 __le32 fuse_ver_offset; 438 __le32 preboot_ver_offset; 439 __le32 uboot_ver_offset; 440 __le32 hw_state; 441 __le32 kmd_msg_to_cpu; 442 __le32 cpu_cmd_status_to_host; 443 __le32 gic_host_pi_upd_irq; 444 __le32 gic_tpc_qm_irq_ctrl; 445 __le32 gic_mme_qm_irq_ctrl; 446 __le32 gic_dma_qm_irq_ctrl; 447 __le32 gic_nic_qm_irq_ctrl; 448 __le32 gic_dma_core_irq_ctrl; 449 __le32 gic_host_halt_irq; 450 __le32 gic_host_ints_irq; 451 __le32 gic_host_soft_rst_irq; 452 __le32 gic_rot_qm_irq_ctrl; 453 __le32 cpu_rst_status; 454 __le32 eng_arc_irq_ctrl; 455 __le32 reserved1[20]; /* reserve for future use */ 456 }; 457 458 /* TODO: remove the desc magic after the code is updated to use message */ 459 /* HCDM - Habana Communications Descriptor Magic */ 460 #define HL_COMMS_DESC_MAGIC 0x4843444D 461 #define HL_COMMS_DESC_VER 3 462 463 /* HCMv - Habana Communications Message + header version */ 464 #define HL_COMMS_MSG_MAGIC_VALUE 0x48434D00 465 #define HL_COMMS_MSG_MAGIC_MASK 0xFFFFFF00 466 #define HL_COMMS_MSG_MAGIC_VER_MASK 0xFF 467 468 #define HL_COMMS_MSG_MAGIC_VER(ver) (HL_COMMS_MSG_MAGIC_VALUE | \ 469 ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK)) 470 #define HL_COMMS_MSG_MAGIC_V0 HL_COMMS_DESC_MAGIC 471 #define HL_COMMS_MSG_MAGIC_V1 HL_COMMS_MSG_MAGIC_VER(1) 472 #define HL_COMMS_MSG_MAGIC_V2 HL_COMMS_MSG_MAGIC_VER(2) 473 #define HL_COMMS_MSG_MAGIC_V3 HL_COMMS_MSG_MAGIC_VER(3) 474 475 #define HL_COMMS_MSG_MAGIC HL_COMMS_MSG_MAGIC_V3 476 477 #define HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC(magic) \ 478 (((magic) & HL_COMMS_MSG_MAGIC_MASK) == \ 479 HL_COMMS_MSG_MAGIC_VALUE) 480 481 #define HL_COMMS_MSG_MAGIC_VALIDATE_VERSION(magic, ver) \ 482 (((magic) & HL_COMMS_MSG_MAGIC_VER_MASK) >= \ 483 ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK)) 484 485 #define HL_COMMS_MSG_MAGIC_VALIDATE(magic, ver) \ 486 (HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC((magic)) && \ 487 HL_COMMS_MSG_MAGIC_VALIDATE_VERSION((magic), (ver))) 488 489 enum comms_msg_type { 490 HL_COMMS_DESC_TYPE = 0, 491 HL_COMMS_RESET_CAUSE_TYPE = 1, 492 HL_COMMS_FW_CFG_SKIP_TYPE = 2, 493 HL_COMMS_BINNING_CONF_TYPE = 3, 494 }; 495 496 /* 497 * Binning information shared between LKD and FW 498 * @tpc_mask_l - TPC binning information lower 64 bit 499 * @dec_mask - Decoder binning information 500 * @dram_mask - DRAM binning information 501 * @edma_mask - EDMA binning information 502 * @mme_mask_l - MME binning information lower 32 503 * @mme_mask_h - MME binning information upper 32 504 * @rot_mask - Rotator binning information 505 * @xbar_mask - xBAR binning information 506 * @reserved - reserved field for future binning info w/o ABI change 507 * @tpc_mask_h - TPC binning information upper 64 bit 508 * @nic_mask - NIC binning information 509 */ 510 struct lkd_fw_binning_info { 511 __le64 tpc_mask_l; 512 __le32 dec_mask; 513 __le32 dram_mask; 514 __le32 edma_mask; 515 __le32 mme_mask_l; 516 __le32 mme_mask_h; 517 __le32 rot_mask; 518 __le32 xbar_mask; 519 __le32 reserved0; 520 __le64 tpc_mask_h; 521 __le64 nic_mask; 522 __le32 reserved1[8]; 523 }; 524 525 /* TODO: remove this struct after the code is updated to use message */ 526 /* this is the comms descriptor header - meta data */ 527 struct comms_desc_header { 528 __le32 magic; /* magic for validation */ 529 __le32 crc32; /* CRC32 of the descriptor w/o header */ 530 __le16 size; /* size of the descriptor w/o header */ 531 __u8 version; /* descriptor version */ 532 __u8 reserved[5]; /* pad to 64 bit */ 533 }; 534 535 /* this is the comms message header - meta data */ 536 struct comms_msg_header { 537 __le32 magic; /* magic for validation */ 538 __le32 crc32; /* CRC32 of the message w/o header */ 539 __le16 size; /* size of the message w/o header */ 540 __u8 version; /* message payload version */ 541 __u8 type; /* message type */ 542 __u8 reserved[4]; /* pad to 64 bit */ 543 }; 544 545 enum lkd_fw_ascii_msg_lvls { 546 LKD_FW_ASCII_MSG_ERR = 0, 547 LKD_FW_ASCII_MSG_WRN = 1, 548 LKD_FW_ASCII_MSG_INF = 2, 549 LKD_FW_ASCII_MSG_DBG = 3, 550 }; 551 552 #define LKD_FW_ASCII_MSG_MAX_LEN 128 553 #define LKD_FW_ASCII_MSG_MAX 4 /* consider ABI when changing */ 554 555 struct lkd_fw_ascii_msg { 556 __u8 valid; 557 __u8 msg_lvl; 558 __u8 reserved[6]; 559 char msg[LKD_FW_ASCII_MSG_MAX_LEN]; 560 }; 561 562 /* this is the main FW descriptor - consider ABI when changing */ 563 struct lkd_fw_comms_desc { 564 struct comms_desc_header header; 565 struct cpu_dyn_regs cpu_dyn_regs; 566 char fuse_ver[VERSION_MAX_LEN]; 567 char cur_fw_ver[VERSION_MAX_LEN]; 568 /* can be used for 1 more version w/o ABI change */ 569 char reserved0[VERSION_MAX_LEN]; 570 __le64 img_addr; /* address for next FW component load */ 571 struct lkd_fw_binning_info binning_info; 572 struct lkd_fw_ascii_msg ascii_msg[LKD_FW_ASCII_MSG_MAX]; 573 }; 574 575 enum comms_reset_cause { 576 HL_RESET_CAUSE_UNKNOWN = 0, 577 HL_RESET_CAUSE_HEARTBEAT = 1, 578 HL_RESET_CAUSE_TDR = 2, 579 }; 580 581 /* TODO: remove define after struct name is aligned on all projects */ 582 #define lkd_msg_comms lkd_fw_comms_msg 583 584 /* this is the comms message descriptor */ 585 struct lkd_fw_comms_msg { 586 struct comms_msg_header header; 587 /* union for future expantions of new messages */ 588 union { 589 struct { 590 struct cpu_dyn_regs cpu_dyn_regs; 591 char fuse_ver[VERSION_MAX_LEN]; 592 char cur_fw_ver[VERSION_MAX_LEN]; 593 /* can be used for 1 more version w/o ABI change */ 594 char reserved0[VERSION_MAX_LEN]; 595 /* address for next FW component load */ 596 __le64 img_addr; 597 struct lkd_fw_binning_info binning_info; 598 struct lkd_fw_ascii_msg ascii_msg[LKD_FW_ASCII_MSG_MAX]; 599 }; 600 struct { 601 __u8 reset_cause; 602 }; 603 struct { 604 __u8 fw_cfg_skip; /* 1 - skip, 0 - don't skip */ 605 }; 606 struct lkd_fw_binning_info binning_conf; 607 }; 608 }; 609 610 /* 611 * LKD commands: 612 * 613 * COMMS_NOOP Used to clear the command register and no actual 614 * command is send. 615 * 616 * COMMS_CLR_STS Clear status command - FW should clear the 617 * status register. Used for synchronization 618 * between the commands as part of the race free 619 * protocol. 620 * 621 * COMMS_RST_STATE Reset the current communication state which is 622 * kept by FW for proper responses. 623 * Should be used in the beginning of the 624 * communication cycle to clean any leftovers from 625 * previous communication attempts. 626 * 627 * COMMS_PREP_DESC Prepare descriptor for setting up the 628 * communication and other dynamic data: 629 * struct lkd_fw_comms_desc. 630 * This command has a parameter stating the next FW 631 * component size, so the FW can actually prepare a 632 * space for it and in the status response provide 633 * the descriptor offset. The Offset of the next FW 634 * data component is a part of the descriptor 635 * structure. 636 * 637 * COMMS_DATA_RDY The FW data has been uploaded and is ready for 638 * validation. 639 * 640 * COMMS_EXEC Execute the next FW component. 641 * 642 * COMMS_RST_DEV Reset the device. 643 * 644 * COMMS_GOTO_WFE Execute WFE command. Allowed only on non-secure 645 * devices. 646 * 647 * COMMS_SKIP_BMC Perform actions required for BMC-less servers. 648 * Do not wait for BMC response. 649 * 650 * COMMS_PREP_DESC_ELBI Same as COMMS_PREP_DESC only that the memory 651 * space is allocated in a ELBI access only 652 * address range. 653 * 654 */ 655 enum comms_cmd { 656 COMMS_NOOP = 0, 657 COMMS_CLR_STS = 1, 658 COMMS_RST_STATE = 2, 659 COMMS_PREP_DESC = 3, 660 COMMS_DATA_RDY = 4, 661 COMMS_EXEC = 5, 662 COMMS_RST_DEV = 6, 663 COMMS_GOTO_WFE = 7, 664 COMMS_SKIP_BMC = 8, 665 COMMS_PREP_DESC_ELBI = 10, 666 COMMS_INVLD_LAST 667 }; 668 669 #define COMMS_COMMAND_SIZE_SHIFT 0 670 #define COMMS_COMMAND_SIZE_MASK 0x1FFFFFF 671 #define COMMS_COMMAND_CMD_SHIFT 27 672 #define COMMS_COMMAND_CMD_MASK 0xF8000000 673 674 /* 675 * LKD command to FW register structure 676 * @size - FW component size 677 * @cmd - command from enum comms_cmd 678 */ 679 struct comms_command { 680 union { /* bit fields are only for FW use */ 681 struct { 682 u32 size :25; /* 32MB max. */ 683 u32 reserved :2; 684 enum comms_cmd cmd :5; /* 32 commands */ 685 }; 686 __le32 val; 687 }; 688 }; 689 690 /* 691 * FW status 692 * 693 * COMMS_STS_NOOP Used to clear the status register and no actual 694 * status is provided. 695 * 696 * COMMS_STS_ACK Command has been received and recognized. 697 * 698 * COMMS_STS_OK Command execution has finished successfully. 699 * 700 * COMMS_STS_ERR Command execution was unsuccessful and resulted 701 * in error. 702 * 703 * COMMS_STS_VALID_ERR FW validation has failed. 704 * 705 * COMMS_STS_TIMEOUT_ERR Command execution has timed out. 706 */ 707 enum comms_sts { 708 COMMS_STS_NOOP = 0, 709 COMMS_STS_ACK = 1, 710 COMMS_STS_OK = 2, 711 COMMS_STS_ERR = 3, 712 COMMS_STS_VALID_ERR = 4, 713 COMMS_STS_TIMEOUT_ERR = 5, 714 COMMS_STS_INVLD_LAST 715 }; 716 717 /* RAM types for FW components loading - defines the base address */ 718 enum comms_ram_types { 719 COMMS_SRAM = 0, 720 COMMS_DRAM = 1, 721 }; 722 723 #define COMMS_STATUS_OFFSET_SHIFT 0 724 #define COMMS_STATUS_OFFSET_MASK 0x03FFFFFF 725 #define COMMS_STATUS_OFFSET_ALIGN_SHIFT 2 726 #define COMMS_STATUS_RAM_TYPE_SHIFT 26 727 #define COMMS_STATUS_RAM_TYPE_MASK 0x0C000000 728 #define COMMS_STATUS_STATUS_SHIFT 28 729 #define COMMS_STATUS_STATUS_MASK 0xF0000000 730 731 /* 732 * FW status to LKD register structure 733 * @offset - an offset from the base of the ram_type shifted right by 734 * 2 bits (always aligned to 32 bits). 735 * Allows a maximum addressable offset of 256MB from RAM base. 736 * Example: for real offset in RAM of 0x800000 (8MB), the value 737 * in offset field is (0x800000 >> 2) = 0x200000. 738 * @ram_type - the RAM type that should be used for offset from 739 * enum comms_ram_types 740 * @status - status from enum comms_sts 741 */ 742 struct comms_status { 743 union { /* bit fields are only for FW use */ 744 struct { 745 u32 offset :26; 746 enum comms_ram_types ram_type :2; 747 enum comms_sts status :4; /* 16 statuses */ 748 }; 749 __le32 val; 750 }; 751 }; 752 753 #define NAME_MAX_LEN 32 /* bytes */ 754 struct hl_module_data { 755 __u8 name[NAME_MAX_LEN]; 756 __u8 version[VERSION_MAX_LEN]; 757 }; 758 759 /** 760 * struct hl_component_versions - versions associated with hl component. 761 * @struct_size: size of all the struct (including dynamic size of modules). 762 * @modules_offset: offset of the modules field in this struct. 763 * @component: version of the component itself. 764 * @fw_os: Firmware OS Version. 765 * @comp_name: Name of the component. 766 * @modules_counter: number of set bits in modules_mask. 767 * @reserved: reserved for future use. 768 * @modules: versions of the component's modules. Elborated explanation in 769 * struct cpucp_versions. 770 */ 771 struct hl_component_versions { 772 __le16 struct_size; 773 __le16 modules_offset; 774 __u8 component[VERSION_MAX_LEN]; 775 __u8 fw_os[VERSION_MAX_LEN]; 776 __u8 comp_name[NAME_MAX_LEN]; 777 __u8 modules_counter; 778 __u8 reserved[3]; 779 struct hl_module_data modules[]; 780 }; 781 782 /* Max size of fit size */ 783 #define HL_FW_VERSIONS_FIT_SIZE 4096 784 785 #endif /* HL_BOOT_IF_H */ 786