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Searched refs:cp_hqd_pq_control (Results 1 – 24 of 24) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/amdkfd/
Dkfd_mqd_manager_cik.c179 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in __update_mqd()
183 m->cp_hqd_pq_control |= PQ_ATC_EN; in __update_mqd()
191 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
201 m->cp_hqd_pq_control |= NO_UPDATE_RPTR; in __update_mqd()
342 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in update_mqd_hiq()
351 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd_hiq()
Dkfd_mqd_manager_v10.c170 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
171 m->cp_hqd_pq_control |= in update_mqd()
173 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in update_mqd()
174 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
212 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
318 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
Dkfd_mqd_manager_v11.c224 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
225 m->cp_hqd_pq_control |= in update_mqd()
227 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in update_mqd()
228 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
266 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
372 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
Dkfd_mqd_manager_v9.c246 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in update_mqd()
247 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd()
248 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
292 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
414 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
535 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in init_mqd_hiq_v9_4_3()
541 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; in init_mqd_hiq_v9_4_3()
657 m->cp_hqd_pq_control &= in init_mqd_v9_4_3()
695 m->cp_hqd_pq_control &= in update_mqd_v9_4_3()
Dkfd_mqd_manager_vi.c178 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | in __update_mqd()
181 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
182 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in __update_mqd()
225 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in __update_mqd()
329 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
/linux-6.6.21/drivers/gpu/drm/amd/include/
Dcik_structs.h96 uint32_t cp_hqd_pq_control; member
Dvi_structs.h305 uint32_t cp_hqd_pq_control; member
Dv9_structs.h315 uint32_t cp_hqd_pq_control; member
Dv11_structs.h820 uint32_t cp_hqd_pq_control; // offset: 145 (0x91) member
Dv10_structs.h822 uint32_t cp_hqd_pq_control; member
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c2778 u32 cp_hqd_pq_control; member
2891 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_mqd_init()
2892 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2896 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2898 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2901 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2904 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2908 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
Damdgpu_amdkfd_gc_9_4_3.c330 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_gfx_v9_4_3_hqd_load()
Dmes_v10_1.c701 mqd->cp_hqd_pq_control = tmp; in mes_v10_1_mqd_init()
778 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
Damdgpu_amdkfd_gfx_v10_3.c240 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in hqd_load_v10_3()
Dmes_v11_0.c778 mqd->cp_hqd_pq_control = tmp; in mes_v11_0_mqd_init()
853 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v11_0_queue_init_register()
Damdgpu_amdkfd_gfx_v11.c225 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in hqd_load_v11()
Damdgpu_amdkfd_gfx_v10.c254 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_hqd_load()
Dgfx_v9_4_3.c1556 mqd->cp_hqd_pq_control = tmp; in gfx_v9_4_3_xcc_mqd_init()
1657 mqd->cp_hqd_pq_control); in gfx_v9_4_3_xcc_kiq_init_register()
1766 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { in gfx_v9_4_3_xcc_kiq_init_queue()
1811 if (!tmp_mqd->cp_hqd_pq_control || in gfx_v9_4_3_xcc_kcq_init_queue()
Damdgpu_amdkfd_gfx_v9.c269 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_gfx_v9_hqd_load()
Dgfx_v9_0.c3334 mqd->cp_hqd_pq_control = tmp; in gfx_v9_0_mqd_init()
3434 mqd->cp_hqd_pq_control); in gfx_v9_0_kiq_init_register()
3543 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ in gfx_v9_0_kiq_init_queue()
3589 if (!tmp_mqd->cp_hqd_pq_control || in gfx_v9_0_kcq_init_queue()
Dgfx_v11_0.c3814 mqd->cp_hqd_pq_control = tmp; in gfx_v11_0_compute_mqd_init()
3931 mqd->cp_hqd_pq_control); in gfx_v11_0_kiq_init_register()
Dgfx_v10_0.c6577 mqd->cp_hqd_pq_control = tmp; in gfx_v10_0_compute_mqd_init()
6676 mqd->cp_hqd_pq_control); in gfx_v10_0_kiq_init_register()
Dgfx_v8_0.c4475 mqd->cp_hqd_pq_control = tmp; in gfx_v8_0_mqd_init()
/linux-6.6.21/drivers/gpu/drm/radeon/
Dcik.c4451 u32 cp_hqd_pq_control; member
4658 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); in cik_cp_compute_resume()
4659 mqd->queue_state.cp_hqd_pq_control &= in cik_cp_compute_resume()
4662 mqd->queue_state.cp_hqd_pq_control |= in cik_cp_compute_resume()
4664 mqd->queue_state.cp_hqd_pq_control |= in cik_cp_compute_resume()
4667 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT; in cik_cp_compute_resume()
4669 mqd->queue_state.cp_hqd_pq_control &= in cik_cp_compute_resume()
4671 mqd->queue_state.cp_hqd_pq_control |= in cik_cp_compute_resume()
4673 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()