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Searched refs:controller_id (Results 1 – 25 of 78) sorted by relevance

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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_hw_sequencer.c78 #define CNTL_ID(controller_id)\
79 controller_id
83 static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
152 uint8_t controller_id, in dce120_enable_display_power_gating() argument
169 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) { in dce120_enable_display_power_gating()
172 dcb, controller_id + 1, cntl); in dce120_enable_display_power_gating()
178 HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id), in dce120_enable_display_power_gating()
183 dce120_init_pte(ctx, controller_id); in dce120_enable_display_power_gating()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/bios/
Dcommand_table.h76 enum controller_id controller_id,
80 enum controller_id controller_id,
90 enum controller_id crtc_id,
Dcommand_table2.h76 enum controller_id controller_id,
80 enum controller_id controller_id,
90 enum controller_id crtc_id,
Dcommand_table2.c441 uint8_t controller_id; in set_pixel_clock_v7() local
448 controller_id, &controller_id)) { in set_pixel_clock_v7()
468 clk.crtc_id = controller_id; in set_pixel_clock_v7()
488 bp_params->target_pixel_clock_100hz, (int)controller_id, in set_pixel_clock_v7()
571 bp_params->controller_id, &atom_controller_id)) in set_crtc_using_dtd_timing_v3()
663 enum controller_id controller_id,
682 enum controller_id controller_id, in enable_crtc_v1() argument
689 if (bp->cmd_helper->controller_id_to_atom(controller_id, &id)) in enable_crtc_v1()
759 enum controller_id crtc_id,
764 enum controller_id crtc_id,
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Dcommand_table.c1019 if (CONTROLLER_ID_D1 != bp_params->controller_id) in set_pixel_clock_v3()
1052 uint8_t controller_id; in set_pixel_clock_v5() local
1059 bp_params->controller_id, &controller_id)) { in set_pixel_clock_v5()
1060 clk.sPCLKInput.ucCRTC = controller_id; in set_pixel_clock_v5()
1122 uint8_t controller_id; in set_pixel_clock_v6() local
1129 bp_params->controller_id, &controller_id)) { in set_pixel_clock_v6()
1149 clk.sPCLKInput.ulCrtcPclkFreq.ucCRTC = controller_id; in set_pixel_clock_v6()
1214 uint8_t controller_id; in set_pixel_clock_v7() local
1220 && bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &controller_id)) { in set_pixel_clock_v7()
1240 clk.ucCRTC = controller_id; in set_pixel_clock_v7()
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/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce/
Ddce_abm.c58 static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst) in dce_abm_set_pipe() argument
75 MASTER_COMM_CMD_REG_BYTE1, controller_id); in dce_abm_set_pipe()
90 uint32_t controller_id, in dmcu_set_backlight_level() argument
103 dce_abm_set_pipe(&abm_dce->base, controller_id, panel_id); in dmcu_set_backlight_level()
113 if (controller_id == 0) in dmcu_set_backlight_level()
234 unsigned int controller_id, in dce_abm_set_backlight_level_pwm() argument
245 controller_id, in dce_abm_set_backlight_level_pwm()
Ddce_clock_source.c859 bp_pc_params.controller_id = pix_clk_params->controller_id; in dce110_program_pix_clk()
933 bp_pc_params.controller_id = pix_clk_params->controller_id; in dce112_program_pix_clk()
968 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; in dcn31_program_pix_clk()
1005 bp_pc_params.controller_id = pix_clk_params->controller_id; in dcn31_program_pix_clk()
1067 bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED; in dce110_clock_source_power_down()
1174 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; in dcn20_program_pix_clk()
1220 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; in dcn3_program_pix_clk()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_hw_sequencer.c74 uint8_t controller_id, in dce100_enable_display_power_gating() argument
89 if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){ in dce100_enable_display_power_gating()
92 dcb, controller_id + 1, cntl); in dce100_enable_display_power_gating()
98 HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id), in dce100_enable_display_power_gating()
Ddce100_hw_sequencer.h45 bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_hw_sequencer.c115 uint8_t controller_id, in dce112_enable_display_power_gating() argument
130 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) { in dce112_enable_display_power_gating()
133 dcb, controller_id + 1, cntl); in dce112_enable_display_power_gating()
139 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), in dce112_enable_display_power_gating()
/linux-6.6.21/drivers/gpu/drm/amd/display/include/
Dbios_parser_types.h137 enum controller_id controller_id; member
170 enum controller_id controller_id; member
218 enum controller_id controller_id; /* (Which CRTC uses this PLL) */ member
Dgrph_object_id.h74 enum controller_id { enum
255 static inline enum controller_id dal_graphics_object_id_get_controller_id( in dal_graphics_object_id_get_controller_id()
259 return (enum controller_id) id.id; in dal_graphics_object_id_get_controller_id()
/linux-6.6.21/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_8_0_sc8280xp.h327 .controller_id = MSM_DP_CONTROLLER_0,
337 .controller_id = MSM_DSI_CONTROLLER_0,
347 .controller_id = MSM_DSI_CONTROLLER_1,
357 .controller_id = MSM_DP_CONTROLLER_0,
367 .controller_id = MSM_DP_CONTROLLER_1,
377 .controller_id = MSM_DP_CONTROLLER_3,
387 .controller_id = MSM_DP_CONTROLLER_2,
397 .controller_id = MSM_DP_CONTROLLER_2,
407 .controller_id = MSM_DP_CONTROLLER_1,
Ddpu_5_1_sc8180x.h313 .controller_id = MSM_DP_CONTROLLER_0,
323 .controller_id = MSM_DSI_CONTROLLER_0,
333 .controller_id = MSM_DSI_CONTROLLER_1,
345 .controller_id = 999,
355 .controller_id = MSM_DP_CONTROLLER_1,
365 .controller_id = MSM_DP_CONTROLLER_2,
Ddpu_4_0_sdm845.h259 .controller_id = MSM_DP_CONTROLLER_0,
268 .controller_id = MSM_DSI_CONTROLLER_0,
277 .controller_id = MSM_DSI_CONTROLLER_1,
286 .controller_id = MSM_DP_CONTROLLER_1,
Ddpu_7_2_sc7280.h193 .controller_id = MSM_DP_CONTROLLER_0,
203 .controller_id = MSM_DSI_CONTROLLER_0,
213 .controller_id = MSM_DP_CONTROLLER_1,
Ddpu_5_0_sm8150.h306 .controller_id = MSM_DP_CONTROLLER_0,
316 .controller_id = MSM_DSI_CONTROLLER_0,
326 .controller_id = MSM_DSI_CONTROLLER_1,
336 .controller_id = MSM_DP_CONTROLLER_1,
Ddpu_6_0_sm8250.h305 .controller_id = MSM_DP_CONTROLLER_0,
315 .controller_id = MSM_DSI_CONTROLLER_0,
325 .controller_id = MSM_DSI_CONTROLLER_1,
335 .controller_id = MSM_DP_CONTROLLER_1,
Ddpu_7_0_sm8350.h329 .controller_id = MSM_DP_CONTROLLER_0,
339 .controller_id = MSM_DSI_CONTROLLER_0,
349 .controller_id = MSM_DSI_CONTROLLER_1,
359 .controller_id = MSM_DP_CONTROLLER_1,
Ddpu_8_1_sm8450.h351 .controller_id = MSM_DP_CONTROLLER_0,
361 .controller_id = MSM_DSI_CONTROLLER_0,
371 .controller_id = MSM_DSI_CONTROLLER_1,
381 .controller_id = MSM_DP_CONTROLLER_1,
Ddpu_9_0_sm8550.h350 .controller_id = MSM_DP_CONTROLLER_0,
360 .controller_id = MSM_DSI_CONTROLLER_0,
370 .controller_id = MSM_DSI_CONTROLLER_1,
380 .controller_id = MSM_DP_CONTROLLER_1,
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/inc/hw/
Dabm.h42 bool (*set_pipe)(struct abm *abm, unsigned int controller_id, unsigned int panel_inst);
50 unsigned int controller_id,
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/
Ddc_bios_types.h102 enum controller_id id,
125 enum controller_id controller_id,
/linux-6.6.21/drivers/scsi/aic94xx/
Daic94xx_sds.h66 struct controller_id { struct
85 struct controller_id contrl_id; /*PCI id to identify the controller */ argument
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/inc/
Dclock_source.h92 enum controller_id controller_id; member

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