Searched refs:cmr (Results 1 – 7 of 7) sorted by relevance
| /linux-6.6.21/drivers/pwm/ |
| D | pwm-atmel-tcb.c | 43 u32 cmr; member
74 unsigned cmr; in atmel_tcb_pwm_request() local
86 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr); in atmel_tcb_pwm_request()
91 if (cmr & ATMEL_TC_WAVE) { in atmel_tcb_pwm_request()
101 tcbpwm->div = cmr & ATMEL_TC_TCCLKS; in atmel_tcb_pwm_request()
104 cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK | in atmel_tcb_pwm_request()
107 cmr = 0; in atmel_tcb_pwm_request()
109 cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0; in atmel_tcb_pwm_request()
110 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr); in atmel_tcb_pwm_request()
128 unsigned cmr; in atmel_tcb_pwm_disable() local
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| D | pwm-atmel.c | 310 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_apply() local
314 pres = cmr & PWM_CMR_CPRE_MSK; in atmel_pwm_apply()
362 u32 sr, cmr; in atmel_pwm_get_state() local
365 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_get_state()
372 pres = cmr & PWM_CMR_CPRE_MSK; in atmel_pwm_get_state()
394 if (cmr & PWM_CMR_CPOL) in atmel_pwm_get_state()
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| /linux-6.6.21/drivers/counter/ |
| D | microchip-tcb-capture.c | 87 u32 bmr, cmr; in mchp_tc_count_function_write() local
90 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr); in mchp_tc_count_function_write()
93 cmr &= ~ATMEL_TC_WAVE; in mchp_tc_count_function_write()
101 cmr |= ATMEL_TC_TIMER_CLOCK2; in mchp_tc_count_function_write()
103 cmr |= ATMEL_TC_TIMER_CLOCK1; in mchp_tc_count_function_write()
105 cmr |= ATMEL_TC_CMR_MASK; in mchp_tc_count_function_write()
106 cmr &= ~(ATMEL_TC_ABETRG | ATMEL_TC_XC0); in mchp_tc_count_function_write()
119 cmr |= ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_ABETRG | ATMEL_TC_XC0; in mchp_tc_count_function_write()
127 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr); in mchp_tc_count_function_write()
135 ATMEL_TC_REG(priv->channel[1], CMR), cmr); in mchp_tc_count_function_write()
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| D | 104-quad-8.c | 62 u8 cmr[QUAD8_NUM_COUNTERS]; member
326 switch (u8_get_bits(priv->cmr[id], QUADRATURE_MODE)) { in quad8_function_get()
402 ret = quad8_control_register_update(priv->map, priv->cmr, id, mode_cfg, QUADRATURE_MODE); in quad8_function_write()
714 switch (u8_get_bits(priv->cmr[count->id], COUNT_MODE)) { in quad8_count_mode_read()
761 ret = quad8_control_register_update(priv->map, priv->cmr, count->id, count_mode, in quad8_count_mode_write()
854 switch (u8_get_bits(priv->cmr[count->id], COUNT_MODE)) { in quad8_count_ceiling_read()
882 switch (u8_get_bits(priv->cmr[count->id], COUNT_MODE)) { in quad8_count_ceiling_write()
1256 priv->cmr[channel] = SELECT_CMR | BINARY | u8_encode_bits(NORMAL_COUNT, COUNT_MODE) | in quad8_init_counter()
1258 ret = regmap_write(priv->map, QUAD8_CONTROL(channel), priv->cmr[channel]); in quad8_init_counter()
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| /linux-6.6.21/drivers/clocksource/ |
| D | timer-atmel-tcb.c | 44 u32 cmr; member
78 tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR)); in tc_clksrc_suspend()
94 writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR)); in tc_clksrc_resume()
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| /linux-6.6.21/drivers/scsi/lpfc/ |
| D | lpfc.h | 223 uint32_t cmr : 1; /* Configure Max RPIs */ member
225 uint32_t cmr : 1; /* Configure Max RPIs */
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| D | lpfc_hw.h | 3462 uint32_t cmr : 1; /* Configure Max RPIs */ member
3464 uint32_t cmr : 1; /* Configure Max RPIs */ member
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