| /linux-6.6.21/drivers/clk/mediatek/ |
| D | clk-mt8183-ipu_conn.c | 16 .clr_ofs = 0x8,
22 .clr_ofs = 0x10,
28 .clr_ofs = 0x18,
34 .clr_ofs = 0x1c,
40 .clr_ofs = 0x20,
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| D | clk-mt8186-vdec.c | 17 .clr_ofs = 0x4,
23 .clr_ofs = 0x190,
29 .clr_ofs = 0x204,
35 .clr_ofs = 0xc,
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| D | clk-mt8195-vdo1.c | 15 .clr_ofs = 0x108,
21 .clr_ofs = 0x128,
27 .clr_ofs = 0x138,
33 .clr_ofs = 0x148,
39 .clr_ofs = 0x400,
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| D | clk-mt8188-vdo1.c | 18 .clr_ofs = 0x108,
24 .clr_ofs = 0x118,
30 .clr_ofs = 0x128,
36 .clr_ofs = 0x138,
42 .clr_ofs = 0x148,
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| D | clk-gate.c | 21 int clr_ofs; member
62 regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit)); in mtk_cg_clr_bit()
158 int clr_ofs, int sta_ofs, u8 bit, in mtk_clk_register_gate() argument
178 cg->clr_ofs = clr_ofs; in mtk_clk_register_gate()
234 gate->regs->clr_ofs, in mtk_clk_register_gates()
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| D | clk-mt7622-aud.c | 33 .clr_ofs = 0x0,
39 .clr_ofs = 0x10,
45 .clr_ofs = 0x14,
51 .clr_ofs = 0x634,
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| D | clk-mt8188-vdec.c | 16 .clr_ofs = 0x4,
22 .clr_ofs = 0x204,
28 .clr_ofs = 0xc,
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| D | clk-mt8192-vdec.c | 17 .clr_ofs = 0x4,
23 .clr_ofs = 0x204,
29 .clr_ofs = 0xc,
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| D | clk-mt8188-infra_ao.c | 17 .clr_ofs = 0x84,
23 .clr_ofs = 0x8c,
29 .clr_ofs = 0xa8,
35 .clr_ofs = 0xc4,
41 .clr_ofs = 0xe4,
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| D | clk-mt2701-aud.c | 32 .clr_ofs = 0x0,
38 .clr_ofs = 0x10,
44 .clr_ofs = 0x14,
50 .clr_ofs = 0x634,
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| D | clk-mt8195-vdec.c | 15 .clr_ofs = 0x4,
21 .clr_ofs = 0x204,
27 .clr_ofs = 0xc,
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| D | clk-mt7986-eth.c | 19 .clr_ofs = 0xe4,
35 .clr_ofs = 0xe4,
51 .clr_ofs = 0x30,
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| D | clk-mt8365.c | 575 .clr_ofs = 0,
581 .clr_ofs = 0x104,
587 .clr_ofs = 0x320,
627 .clr_ofs = 0x84,
633 .clr_ofs = 0x8c,
639 .clr_ofs = 0xa8,
645 .clr_ofs = 0xc4,
651 .clr_ofs = 0xd4,
756 .clr_ofs = 0x20c,
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| D | clk-mt8195-infra_ao.c | 16 .clr_ofs = 0x84,
22 .clr_ofs = 0x8c,
28 .clr_ofs = 0xa8,
34 .clr_ofs = 0xc4,
40 .clr_ofs = 0xe4,
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| D | clk-mt7981-eth.c | 21 .clr_ofs = 0xE4,
43 .clr_ofs = 0xE4,
65 .clr_ofs = 0x30,
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| D | clk-mt8188-wpe.c | 18 .clr_ofs = 0x0,
24 .clr_ofs = 0x58,
30 .clr_ofs = 0x5c,
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| D | clk-mt8188-vdo0.c | 18 .clr_ofs = 0x108,
24 .clr_ofs = 0x118,
30 .clr_ofs = 0x128,
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| D | clk-mt8192-mm.c | 16 .clr_ofs = 0x108,
22 .clr_ofs = 0x118,
28 .clr_ofs = 0x1a8,
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| D | clk-mt8195-vpp0.c | 15 .clr_ofs = 0x28,
21 .clr_ofs = 0x34,
27 .clr_ofs = 0x40,
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| D | clk-mt8192-aud.c | 17 .clr_ofs = 0x0,
23 .clr_ofs = 0x4,
29 .clr_ofs = 0x8,
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| D | clk-mt8188-vpp0.c | 16 .clr_ofs = 0x28,
22 .clr_ofs = 0x34,
28 .clr_ofs = 0x40,
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| D | clk-mt8195-vdo0.c | 15 .clr_ofs = 0x108,
21 .clr_ofs = 0x118,
27 .clr_ofs = 0x128,
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| D | clk-mt6795-vdecsys.c | 19 .clr_ofs = 0x0004,
25 .clr_ofs = 0x000c,
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| D | clk-mt2712-mm.c | 17 .clr_ofs = 0x108,
23 .clr_ofs = 0x118,
29 .clr_ofs = 0x228,
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| D | clk-mt8195-wpe.c | 15 .clr_ofs = 0x0,
21 .clr_ofs = 0x58,
27 .clr_ofs = 0x5c,
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