Home
last modified time | relevance | path

Searched refs:clocks (Results 1 – 25 of 2154) sorted by relevance

12345678910>>...87

/linux-6.6.21/arch/arm64/boot/dts/xilinx/
Dzynqmp-clk-ccf.dtsi54 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
62 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
66 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
70 clocks = <&zynqmp_clk ACPU>;
74 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
78 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
82 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
86 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
90 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
94 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
[all …]
/linux-6.6.21/arch/arm/boot/dts/samsung/
Ds5pv210.dtsi82 clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
94 clocks: clock-controller@e0100000 { label
98 clocks = <&xxti>, <&xusbxti>;
125 clocks = <&clocks CLK_PDMA0>;
135 clocks = <&clocks CLK_PDMA1>;
145 clocks = <&clocks CLK_TSADC>;
158 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
174 clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
188 clocks = <&clocks CLK_KEYIF>;
198 clocks = <&clocks CLK_I2C0>;
[all …]
Ds3c64xx.dtsi68 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
69 <&clocks SCLK_MMC0>;
79 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
80 <&clocks SCLK_MMC1>;
90 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
91 <&clocks SCLK_MMC2>;
101 clocks = <&clocks PCLK_WDT>;
110 clocks = <&clocks PCLK_IIC0>;
123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
124 <&clocks SCLK_UART>;
[all …]
/linux-6.6.21/arch/arm/boot/dts/ti/omap/
Domap24xx-clocks.dtsi11 clocks = <&func_96m_ck>, <&mcbsp_clks>;
19 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
25 clocks = <&func_96m_ck>, <&mcbsp_clks>;
33 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
77 clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
85 clocks = <&aplls_clkin_ck>;
93 clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
102 clocks = <&osc_ck>;
124 clocks = <&sys_ck>, <&sys_ck>;
131 clocks = <&sys_ck>;
[all …]
Domap3xxx-clocks.dtsi17 …clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck…
24 clocks = <&osc_sys_ck>;
34 clocks = <&osc_sys_ck>;
42 clocks = <&dpll3_ck>;
50 clocks = <&dpll3_m2_ck>;
58 clocks = <&dpll4_ck>;
66 clocks = <&dpll3_m2x2_ck>;
74 clocks = <&sys_ck>;
92 clocks = <&core_96m_fck>, <&mcbsp_clks>;
100 clocks = <&per_96m_fck>, <&mcbsp_clks>;
[all …]
Domap2430-clocks.dtsi12 clocks = <&func_96m_ck>, <&mcbsp_clks>;
19 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
25 clocks = <&func_96m_ck>, <&mcbsp_clks>;
33 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
39 clocks = <&func_96m_ck>, <&mcbsp_clks>;
47 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
55 clocks = <&dsp_fck>;
63 clocks = <&dsp_fck>;
73 clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
79 clocks = <&core_ck>;
[all …]
Domap2420-clocks.dtsi12 clocks = <&core_ck>;
20 clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
28 clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
34 clocks = <&sys_clkout2_src>;
44 clocks = <&dsp_fck>;
52 clocks = <&dsp_fck>;
62 clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
68 clocks = <&core_ck>;
76 clocks = <&core_ck>;
85 clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
[all …]
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi11 clocks = <&corex2_fck>;
19 clocks = <&corex2_fck>;
28 clocks = <&sys_ck>, <&sys_ck>;
37 clocks = <&dpll5_ck>;
46 clocks = <&core_ck>;
54 clocks = <&core_ck>;
62 clocks = <&core_ck>;
70 clocks = <&core_ck>;
78 clocks = <&dpll4_m2x2_ck>;
86 clocks = <&core_ck>;
[all …]
Domap54xx-clocks.dtsi19 clocks = <&pad_clks_src_ck>;
42 clocks = <&slimbus_src_clk>;
121 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
129 clocks = <&dpll_abe_ck>;
136 clocks = <&dpll_abe_x2_ck>;
146 clocks = <&dpll_abe_m2x2_ck>;
155 clocks = <&dpll_abe_m2x2_ck>;
165 clocks = <&aess_fclk>;
175 clocks = <&dpll_abe_m2x2_ck>;
184 clocks = <&dpll_abe_x2_ck>;
[all …]
Domap34xx-omap36xx-clocks.dtsi11 clocks = <&l4_ick>;
26 clocks = <&security_l4_ick2>;
34 clocks = <&security_l4_ick2>;
42 clocks = <&security_l4_ick2>;
50 clocks = <&security_l4_ick2>;
58 clocks = <&security_l3_ick>;
74 clocks = <&dpll4_m5x2_ck>;
83 clocks = <&core_96m_fck>;
91 clocks = <&l4_ick>;
99 clocks = <&l3_ick>;
[all …]
Ddm816x-clocks.dtsi8 clocks = <&sys_clkin_ck &sys_clkin_ck>;
24 clocks = <&sys_clkin_ck &sys_clkin_ck>;
36 clocks = <&sys_clkin_ck &sys_clkin_ck>;
47 clocks = <&main_fapll 7>, < &sys_clkin_ck>;
88 clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
96 clocks = <&clkout_pre_ck>;
105 clocks = <&clkout_div_ck>;
110 /* CM_DPLL clocks p1795 */
114 clocks = <&main_fapll 1>;
122 clocks = <&main_fapll 2>;
[all …]
/linux-6.6.21/Documentation/devicetree/bindings/clock/
Dsamsung,exynos5433-clock.yaml16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
20 All available clocks are defined as preprocessor macros in
26 # CMU_TOP which generates clocks for
28 # clocks
30 # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP
32 # CMU_MIF which generates clocks for DRAM Memory Controller domain
34 # CMU_PERIC which generates clocks for
37 # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
39 # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
42 # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
[all …]
Drenesas,cpg-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
24 - const: renesas,r8a7778-cpg-clocks # R-Car M1
25 - const: renesas,r8a7779-cpg-clocks # R-Car H1
28 - renesas,r7s72100-cpg-clocks # RZ/A1H
29 - const: renesas,rz-cpg-clocks # RZ/A1
30 - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
35 clocks: true
[all …]
Dsamsung,exynos5260-clock.yaml16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
24 Phy clocks::
25 There are several clocks which are generated by specific PHYs. These clocks
27 These clocks are defined as fixed clocks in the driver with following names::
44 All available clocks are defined as preprocessor macros in
64 clocks:
91 clocks:
102 - clocks
111 clocks:
131 - clocks
[all …]
/linux-6.6.21/tools/testing/selftests/timens/
Dtimens.c37 static struct test_clock clocks[] = { variable
94 if (check_skip(clocks[clock_index].id)) in test_gettime()
97 switch (clocks[clock_index].id) { in test_gettime()
107 if (_gettime(clocks[clock_index].id, &parent_ts_old, raw_syscall)) in test_gettime()
116 if (_gettime(clocks[clock_index].id, &cur_ts, raw_syscall)) in test_gettime()
122 clocks[clock_index].name, entry, parent_ts_old.tv_sec, in test_gettime()
130 if (_gettime(clocks[clock_index].id, &cur_ts, raw_syscall)) in test_gettime()
136 clocks[clock_index].name, entry, parent_ts_old.tv_sec, in test_gettime()
139 clock_settime(clocks[clock_index].id, &cur_ts); in test_gettime()
144 clocks[clock_index].name, entry); in test_gettime()
[all …]
/linux-6.6.21/drivers/clk/mediatek/
DKconfig27 This driver supports MediaTek MT2701 basic clocks.
33 This driver supports MediaTek MT2701 mmsys clocks.
39 This driver supports MediaTek MT2701 imgsys clocks.
45 This driver supports MediaTek MT2701 vdecsys clocks.
51 This driver supports MediaTek MT2701 hifsys clocks.
57 This driver supports MediaTek MT2701 ethsys clocks.
63 This driver supports MediaTek MT2701 bdpsys clocks.
69 This driver supports Mediatek MT2701 audsys clocks.
75 This driver supports MediaTek MT2701 g3dsys clocks.
83 This driver supports MediaTek MT2712 basic clocks.
[all …]
/linux-6.6.21/arch/arm/boot/dts/st/
Dste-nomadik-stn8815.dtsi40 clocks = <&timclk>, <&pclk>;
49 clocks = <&timclk>, <&pclk>;
64 clocks = <&pclk>;
78 clocks = <&pclk>;
92 clocks = <&pclk>;
107 clocks = <&pclk>;
215 clocks = <&mxtal>;
223 clocks = <&mxtal>;
230 clocks = <&pll1>;
238 clocks = <&hclk>;
[all …]
/linux-6.6.21/arch/arm/boot/dts/intel/socfpga/
Dsocfpga.dtsi83 clocks = <&l4_main_clk>;
102 clocks = <&can0_clk>;
111 clocks = <&can1_clk>;
120 clocks {
149 clocks = <&osc1>;
155 clocks = <&main_pll>;
163 clocks = <&main_pll>;
171 clocks = <&main_pll>, <&osc1>;
179 clocks = <&main_pll>;
186 clocks = <&main_pll>;
[all …]
/linux-6.6.21/arch/arm/boot/dts/vt8500/
Dwm8750.dtsi75 clocks {
94 clocks = <&ref25>;
101 clocks = <&ref25>;
108 clocks = <&ref25>;
115 clocks = <&ref25>;
122 clocks = <&ref25>;
129 clocks = <&plla>;
136 clocks = <&pllb>;
143 clocks = <&pllb>;
150 clocks = <&plld>;
[all …]
/linux-6.6.21/arch/arm/boot/dts/renesas/
Dsh73a0.dtsi27 clocks = <&cpg_clocks SH73A0_CLK_Z>;
36 clocks = <&cpg_clocks SH73A0_CLK_Z>;
46 clocks = <&periph_clk>;
53 clocks = <&periph_clk>;
105 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
128 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
150 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
172 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
194 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
208 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
[all …]
Dr7s72100.dtsi30 /* Fixed factor clocks */
34 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
48 clocks = <&cpg_clocks R7S72100_CLK_I>;
53 /* External clocks */
64 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
72 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
121 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
134 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
147 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
160 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
[all …]
/linux-6.6.21/arch/arm/boot/dts/ti/keystone/
Dkeystone-clocks.dtsi8 clocks {
16 clocks = <&mainpllclk>, <&refclksys>;
26 clocks = <&mainmuxclk>;
35 clocks = <&mainmuxclk>;
44 clocks = <&mainmuxclk>;
54 clocks = <&mainmuxclk>;
64 clocks = <&chipclk1>;
73 clocks = <&chipclk1>;
82 clocks = <&papllclk>;
91 clocks = <&chipclk1>;
[all …]
/linux-6.6.21/Documentation/devicetree/bindings/clock/ti/davinci/
Dda8xx-cfgchip.txt1 Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
5 gates. This document describes the bindings for those clocks.
10 USB PHY clocks
13 - compatible: shall be "ti,da830-usb-phy-clocks".
15 - clocks: phandles to the parent clocks corresponding to clock-names
18 This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
26 - clocks: phandle to the parent clock
34 - clocks: phandle to the parent clock
42 - clocks: phandles to the parent clocks corresponding to clock-names
50 - clocks: phandles to the parent clocks corresponding to clock-names
[all …]
/linux-6.6.21/arch/arm64/boot/dts/freescale/
Dimx8-ss-dma.dtsi30 clocks = <&spi0_lpcg 0>,
33 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
46 clocks = <&spi1_lpcg 0>,
49 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
62 clocks = <&spi2_lpcg 0>,
65 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
78 clocks = <&spi3_lpcg 0>,
81 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
90 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
93 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
[all …]
/linux-6.6.21/Documentation/devicetree/bindings/display/
Dst,stih4xx.txt15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names: names of the clocks listed in clocks property in the same
33 - clocks: from common clock binding: handle hardware IP needed clocks, the
34 number of clocks may depend of the SoC type.
35 See ../clocks/clock-bindings.txt for details.
36 - clock-names: names of the clocks listed in clocks property in the same
66 - clocks: from common clock binding: handle hardware IP needed clocks, the
67 number of clocks may depend of the SoC type.
[all …]

12345678910>>...87