Searched refs:clk_div_mask (Results 1 – 14 of 14) sorted by relevance
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()55 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate()91 val &= ~(clk_div_mask(div->width) << div->shift); in clk_divider_gate_set_rate()137 val &= clk_div_mask(div->width); in clk_divider_disable()150 val &= clk_div_mask(div->width); in clk_divider_is_enabled()210 val &= clk_div_mask(width); in imx_clk_hw_divider_gate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()44 div_value &= clk_div_mask(PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()110 val = orig & ~((clk_div_mask(divider->width) << divider->shift) | in imx8m_clk_composite_divider_set_rate()111 (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); in imx8m_clk_composite_divider_set_rate()137 prediv_value &= clk_div_mask(divider->width); in imx8m_divider_determine_rate()141 div_value &= clk_div_mask(PCG_DIV_WIDTH); in imx8m_divider_determine_rate()
123 val &= ~(clk_div_mask(divider->width) << divider->shift); in imx93_clk_composite_divider_set_rate()
48 unsigned int maxdiv = 0, mask = clk_div_mask(width); in _get_table_maxdiv()72 return clk_div_mask(width); in _get_maxdiv()74 return 1 << clk_div_mask(width); in _get_maxdiv()77 return clk_div_mask(width) + 1; in _get_maxdiv()99 return val ? val : clk_div_mask(width) + 1; in _get_div()124 return (div == clk_div_mask(width) + 1) ? 0 : div; in _get_val()156 val &= clk_div_mask(divider->width); in clk_divider_recalc_rate()438 val &= clk_div_mask(divider->width); in clk_divider_round_rate()459 val &= clk_div_mask(divider->width); in clk_divider_determine_rate()483 return min_t(unsigned int, value, clk_div_mask(width)); in divider_get_val()[all …]
76 clk_div_mask(LOONGSON2_PLL_MULT_WIDTH); in loongson2_calc_pll_rate()78 clk_div_mask(LOONGSON2_PLL_DIV_WIDTH); in loongson2_calc_pll_rate()141 mult = (val >> shift) & clk_div_mask(width); in loongson2_calc_rate()
90 val &= clk_div_mask(d->width); in ls1x_divider_recalc_rate()130 val &= ~(clk_div_mask(d->width) << d->shift); in ls1x_divider_set_rate()
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()399 val &= clk_div_mask(divider->width); in m10v_clk_divider_round_rate()430 val &= ~(clk_div_mask(divider->width) << divider->shift); in m10v_clk_divider_set_rate()
602 val &= clk_div_mask(div->width); in bm1880_clk_div_recalc_rate()622 val &= clk_div_mask(div->width); in bm1880_clk_div_round_rate()654 val &= ~(clk_div_mask(div->width) << div_hw->div.shift); in bm1880_clk_div_set_rate()
105 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()107 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()109 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); in mpfs_clk_msspll_recalc_rate()123 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); in mpfs_clk_msspll_round_rate()125 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); in mpfs_clk_msspll_round_rate()144 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); in mpfs_clk_msspll_set_rate()146 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); in mpfs_clk_msspll_set_rate()158 postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); in mpfs_clk_msspll_set_rate()
81 mult &= clk_div_mask(MPFS_CCC_FBDIV_WIDTH); in mpfs_ccc_pll_recalc_rate()83 ref_div &= clk_div_mask(MPFS_CCC_REFDIV_WIDTH); in mpfs_ccc_pll_recalc_rate()
36 val &= clk_div_mask(dclk->width); in ma35d1_clkdiv_recalc_rate()63 data &= ~(clk_div_mask(dclk->width) << dclk->shift); in ma35d1_clkdiv_set_rate()96 max_div = clk_div_mask(width) + 1; in ma35d1_reg_adc_clkdiv()
73 val &= clk_div_mask(div->width); in clk_regmap_div_recalc_rate()93 val &= clk_div_mask(div->width); in clk_regmap_div_determine_rate()118 clk_div_mask(div->width) << div->shift, val); in clk_regmap_div_set_rate()
215 val &= clk_div_mask(divider->width); in stm32_divider_get_rate()243 val = clk_div_mask(divider->width) << (divider->shift + 16); in stm32_divider_set_rate()246 val &= ~(clk_div_mask(divider->width) << divider->shift); in stm32_divider_set_rate()368 val &= clk_div_mask(divider->width); in clk_stm32_divider_round_rate()446 val &= clk_div_mask(divider->width); in clk_stm32_composite_determine_rate()
689 #define clk_div_mask(width) ((1 << (width)) - 1) macro