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Searched refs:clidr (Results 1 – 5 of 5) sorted by relevance

/linux-6.6.21/arch/arm64/include/asm/
Dcache.h15 #define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7) argument
16 #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7) argument
17 #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7) argument
22 #define CLIDR_CTYPE(clidr, level) \ argument
23 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
117 u64 clidr = read_sysreg(clidr_el1); in read_cpuid_effective_cachetype() local
119 if (CLIDR_LOC(clidr) == 0 || in read_cpuid_effective_cachetype()
120 (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0)) in read_cpuid_effective_cachetype()
/linux-6.6.21/arch/arm64/kernel/
Dcacheinfo.c26 u64 clidr; in get_cache_type() local
30 clidr = read_sysreg(clidr_el1); in get_cache_type()
31 return CLIDR_CTYPE(clidr, level); in get_cache_type()
/linux-6.6.21/arch/arm/mm/
Dcache-v7.S100 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
103 ands r3, r3, #7 << 1 @ extract LoU*2 field from clidr
128 mrc p15, 1, r0, c0, c0, 1 @ read clidr
130 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
136 mov r1, r0, lsr r2 @ extract cache type bits from clidr
Dcache-v7m.S178 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
184 mov r1, r0, lsr r2 @ extract cache type bits from clidr
/linux-6.6.21/arch/arm64/kvm/
Dsys_regs.c1663 u64 clidr; in reset_clidr() local
1676 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); in reset_clidr()
1684 clidr = 1 << CLIDR_LOUU_SHIFT; in reset_clidr()
1685 clidr |= 1 << CLIDR_LOUIS_SHIFT; in reset_clidr()
1686 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); in reset_clidr()
1695 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); in reset_clidr()
1697 clidr |= loc << CLIDR_LOC_SHIFT; in reset_clidr()
1705 clidr |= 2 << CLIDR_TTYPE_SHIFT(loc); in reset_clidr()
1707 __vcpu_sys_reg(vcpu, r->reg) = clidr; in reset_clidr()