Home
last modified time | relevance | path

Searched refs:cfgcr0 (Results 1 – 4 of 4) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.h201 u32 cfgcr0; member
Dintel_dpll_mgr.c2730 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * in icl_ddi_combo_pll_get_freq()
2733 dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> in icl_ddi_combo_pll_get_freq()
2756 pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) | in icl_calc_dpll_state()
3553 hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3556 hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3559 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3564 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3575 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3580 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3640 intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0); in icl_dpll_write()
[all …]
Dintel_display_debugfs.c667 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); in i915_shared_dplls_info()
Dintel_display.c5325 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); in intel_pipe_config_compare()