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Searched refs:cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL (Results 1 – 2 of 2) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_2_3_offset.h806 #define cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL … macro
Dnbio_4_3_0_offset.h2652 #define cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL … macro