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Searched refs:cdiv (Results 1 – 7 of 7) sorted by relevance

/linux-6.6.21/drivers/clk/qcom/
Dgcc-ipq4019.c31 struct clk_fepll, cdiv)
73 struct clk_regmap_div cdiv; member
91 u32 fdbkdiv, refclkdiv, cdiv; in clk_fepll_vco_calc_rate() local
94 regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv); in clk_fepll_vco_calc_rate()
95 refclkdiv = (cdiv >> pll_vco->refclkdiv_shift) & in clk_fepll_vco_calc_rate()
97 fdbkdiv = (cdiv >> pll_vco->fdbkdiv_shift) & in clk_fepll_vco_calc_rate()
161 mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift; in clk_cpu_div_set_rate()
162 regmap_update_bits(pll->cdiv.clkr.regmap, in clk_cpu_div_set_rate()
163 pll->cdiv.reg, mask, in clk_cpu_div_set_rate()
164 f->pre_div << pll->cdiv.shift); in clk_cpu_div_set_rate()
[all …]
/linux-6.6.21/drivers/gpu/drm/mcde/
Dmcde_clk_div.c19 struct mcde_clk_div *cdiv = container_of(hw, struct mcde_clk_div, hw); in mcde_clk_div_enable() local
20 struct mcde *mcde = cdiv->mcde; in mcde_clk_div_enable()
24 val = readl(mcde->regs + cdiv->cr); in mcde_clk_div_enable()
36 val |= cdiv->cr_div; in mcde_clk_div_enable()
38 writel(val, mcde->regs + cdiv->cr); in mcde_clk_div_enable()
85 struct mcde_clk_div *cdiv = container_of(hw, struct mcde_clk_div, hw); in mcde_clk_div_recalc_rate() local
86 struct mcde *mcde = cdiv->mcde; in mcde_clk_div_recalc_rate()
98 cr = readl(mcde->regs + cdiv->cr); in mcde_clk_div_recalc_rate()
112 struct mcde_clk_div *cdiv = container_of(hw, struct mcde_clk_div, hw); in mcde_clk_div_set_rate() local
127 cdiv->cr_div = cr; in mcde_clk_div_set_rate()
/linux-6.6.21/drivers/clk/at91/
Dclk-sam9x60-pll.c361 unsigned int val, cdiv; in sam9x60_div_pll_set() local
367 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_set()
370 if (!!(val & core->layout->endiv_mask) && cdiv == div->div) in sam9x60_div_pll_set()
505 unsigned int val, cdiv; in sam9x60_div_pll_set_rate_chg() local
513 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_set_rate_chg()
516 if (cdiv == div->div) in sam9x60_div_pll_set_rate_chg()
553 u32 val, cdiv; in sam9x60_div_pll_notifier_fn() local
569 cdiv = (val & core.layout->div_mask) >> core.layout->div_shift; in sam9x60_div_pll_notifier_fn()
572 if (cdiv == div->safe_div) in sam9x60_div_pll_notifier_fn()
/linux-6.6.21/drivers/spi/
Dspi-bcm2835.c1054 unsigned long spi_hz, cdiv; in bcm2835_spi_transfer_one() local
1062 cdiv = 2; /* clk_hz/2 is the fastest we can go */ in bcm2835_spi_transfer_one()
1065 cdiv = DIV_ROUND_UP(bs->clk_hz, spi_hz); in bcm2835_spi_transfer_one()
1066 cdiv += (cdiv % 2); in bcm2835_spi_transfer_one()
1068 if (cdiv >= 65536) in bcm2835_spi_transfer_one()
1069 cdiv = 0; /* 0 is the slowest we can go */ in bcm2835_spi_transfer_one()
1071 cdiv = 0; /* 0 is the slowest we can go */ in bcm2835_spi_transfer_one()
1073 tfr->effective_speed_hz = cdiv ? (bs->clk_hz / cdiv) : (bs->clk_hz / 65536); in bcm2835_spi_transfer_one()
1074 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv); in bcm2835_spi_transfer_one()
Dspi-ingenic.c104 u32 cdiv, speed_hz = xfer->speed_hz ?: spi->max_speed_hz, in spi_ingenic_prepare_transfer() local
107 cdiv = clk_hz / (speed_hz * 2); in spi_ingenic_prepare_transfer()
108 cdiv = clamp(cdiv, 1u, 0x100u) - 1; in spi_ingenic_prepare_transfer()
110 regmap_write(priv->map, REG_SSIGR, cdiv); in spi_ingenic_prepare_transfer()
/linux-6.6.21/drivers/i2c/busses/
Di2c-at91-master.c68 int ckdiv, cdiv, div, hold = 0, filter_width = 0; in at91_calc_twi_clock() local
79 cdiv = div >> ckdiv; in at91_calc_twi_clock()
85 cdiv = 255; in at91_calc_twi_clock()
122 dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv in at91_calc_twi_clock()
128 cdiv, ckdiv, hold, t->sda_hold_ns, filter_width, in at91_calc_twi_clock()
/linux-6.6.21/drivers/mmc/host/
Dbcm2835.c165 u32 cdiv; member
268 writel(host->cdiv, host->ioaddr + SDCDIV); in bcm2835_reset_internal()
1122 host->cdiv = SDCDIV_MAX_CDIV; in bcm2835_set_clock()
1123 writel(host->cdiv, host->ioaddr + SDCDIV); in bcm2835_set_clock()
1145 host->cdiv = div; in bcm2835_set_clock()
1146 writel(host->cdiv, host->ioaddr + SDCDIV); in bcm2835_set_clock()