/linux-6.6.21/drivers/gpio/ |
D | gpio-omap.c | 78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); 84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument 109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument 112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction() 118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument 121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg() 125 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg() 126 bank->context.dataout |= l; in omap_set_gpio_dataout_reg() 128 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg() 129 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg() [all …]
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D | gpio-rockchip.c | 76 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument 79 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel() 81 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel() 87 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument 90 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl() 93 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl() 101 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument 105 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit() 108 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_writel_bit() 123 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_readl_bit() argument [all …]
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D | gpio-brcmstb.c | 26 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument 27 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument 28 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument 29 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument 30 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument 31 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument 32 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument 33 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument 34 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument 66 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local [all …]
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D | gpio-aspeed-sgpio.c | 105 const struct aspeed_sgpio_bank *bank, in bank_reg() argument 110 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg() 112 return gpio->base + bank->rdata_reg; in bank_reg() 114 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg() 116 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg() 118 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg() 120 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg() 122 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg() 124 return gpio->base + bank->tolerance_regs; in bank_reg() 137 unsigned int bank; in to_bank() local [all …]
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D | gpio-f7188x.c | 95 struct f7188x_gpio_bank *bank; member 291 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); in f7188x_gpio_get_direction() local 292 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_get_direction() 300 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase)); in f7188x_gpio_get_direction() 316 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); in f7188x_gpio_direction_in() local 317 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_direction_in() 325 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase)); in f7188x_gpio_direction_in() 331 superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir); in f7188x_gpio_direction_in() 341 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); in f7188x_gpio_get() local 342 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_get() [all …]
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/linux-6.6.21/drivers/pinctrl/renesas/ |
D | sh_pfc.h | 441 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument 442 fn(bank, pin, GP_##bank##_##pin, sfx, cfg) 443 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument 445 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument 446 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \ 447 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg) 448 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) argument 450 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument 451 PORT_GP_CFG_2(bank, fn, sfx, cfg), \ 452 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \ [all …]
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/linux-6.6.21/drivers/pinctrl/samsung/ |
D | pinctrl-exynos.c | 54 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local 55 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask() 59 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask() 61 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask() 63 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask() 65 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask() 72 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_ack() local 73 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack() 75 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack() 82 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_unmask() local [all …]
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D | pinctrl-samsung.c | 359 struct samsung_pin_bank **bank) in pin_to_reg_bank() argument 371 if (bank) in pin_to_reg_bank() 372 *bank = b; in pin_to_reg_bank() 381 struct samsung_pin_bank *bank; in samsung_pinmux_setup() local 393 ®, &pin_offset, &bank); in samsung_pinmux_setup() 394 type = bank->type; in samsung_pinmux_setup() 403 raw_spin_lock_irqsave(&bank->slock, flags); in samsung_pinmux_setup() 410 raw_spin_unlock_irqrestore(&bank->slock, flags); in samsung_pinmux_setup() 436 struct samsung_pin_bank *bank; in samsung_pinconf_rw() local 445 &pin_offset, &bank); in samsung_pinconf_rw() [all …]
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D | pinctrl-s3c64xx.c | 213 struct samsung_pin_bank *bank; member 268 struct samsung_pin_bank *bank, int pin) in s3c64xx_irq_set_function() argument 270 const struct samsung_pin_bank_type *bank_type = bank->type; in s3c64xx_irq_set_function() 278 reg = d->virt_base + bank->pctl_offset; in s3c64xx_irq_set_function() 289 raw_spin_lock_irqsave(&bank->slock, flags); in s3c64xx_irq_set_function() 293 val |= bank->eint_func << shift; in s3c64xx_irq_set_function() 296 raw_spin_unlock_irqrestore(&bank->slock, flags); in s3c64xx_irq_set_function() 305 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in s3c64xx_gpio_irq_set_mask() local 306 struct samsung_pinctrl_drv_data *d = bank->drvdata; in s3c64xx_gpio_irq_set_mask() 307 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_set_mask() [all …]
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/linux-6.6.21/drivers/crypto/intel/qat/qat_common/ |
D | adf_transport.c | 40 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument 42 spin_lock(&bank->lock); in adf_reserve_ring() 43 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring() 44 spin_unlock(&bank->lock); in adf_reserve_ring() 47 bank->ring_mask |= (1 << ring); in adf_reserve_ring() 48 spin_unlock(&bank->lock); in adf_reserve_ring() 52 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument 54 spin_lock(&bank->lock); in adf_unreserve_ring() 55 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring() 56 spin_unlock(&bank->lock); in adf_unreserve_ring() [all …]
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D | adf_gen4_hw_data.h | 28 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument 30 ADF_RING_BUNDLE_SIZE * (bank) + \ 32 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument 34 ADF_RING_BUNDLE_SIZE * (bank) + \ 36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument 38 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT) 39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument 41 ADF_RING_BUNDLE_SIZE * (bank) + \ 43 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument 46 u32 _bank = bank; \ [all …]
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D | adf_transport_debug.c | 44 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local 45 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev); in adf_ring_show() 46 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show() 51 head = csr_ops->read_csr_ring_head(csr, bank->bank_number, in adf_ring_show() 53 tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number, in adf_ring_show() 55 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show() 61 ring->ring_number, ring->bank->bank_number); in adf_ring_show() 104 ring->bank->bank_debug_dir, in adf_ring_debugfs_add() 121 struct adf_etr_bank_data *bank = sfile->private; in adf_bank_start() local 122 u8 num_rings_per_bank = GET_NUM_RINGS_PER_BANK(bank->accel_dev); in adf_bank_start() [all …]
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D | adf_gen2_hw_data.h | 31 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument 32 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 34 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument 35 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 37 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument 38 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 40 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument 41 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 43 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument 48 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ [all …]
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D | adf_gen4_hw_data.c | 13 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument 15 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head() 18 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument 21 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head() 24 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument 26 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail() 29 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument 32 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail() 35 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument 37 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat() [all …]
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D | adf_gen2_hw_data.c | 119 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument 121 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head() 124 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument 127 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head() 130 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument 132 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail() 135 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument 138 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail() 141 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument 143 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat() [all …]
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/linux-6.6.21/arch/x86/kernel/cpu/mce/ |
D | amd.c | 145 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument 149 if (bank >= MAX_NR_BANKS) in smca_get_bank_type() 152 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type() 252 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) in smca_set_misc_banks_map() argument 260 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) in smca_set_misc_banks_map() 266 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) in smca_set_misc_banks_map() 270 per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank); in smca_set_misc_banks_map() 274 static void smca_configure(unsigned int bank, unsigned int cpu) in smca_configure() argument 280 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); in smca_configure() 309 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); in smca_configure() [all …]
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/linux-6.6.21/tools/testing/selftests/gpio/ |
D | gpio-sim.sh | 181 create_bank chip bank 183 test -n `cat $CONFIGFS_DIR/chip/bank/chip_name` || fail "chip_name doesn't work" 188 create_bank chip bank 195 create_bank chip bank 204 create_bank chip bank 211 create_bank chip bank 212 set_num_lines chip bank 16 219 create_bank chip bank 220 set_label chip bank foobar 227 create_bank chip bank [all …]
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/linux-6.6.21/drivers/pinctrl/stm32/ |
D | pinctrl-stm32.c | 157 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument 160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value() 161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value() 164 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument 167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode() 169 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode() 170 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode() 173 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument 176 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving() 177 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving() [all …]
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/linux-6.6.21/drivers/net/phy/mscc/ |
D | mscc_macsec.c | 23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument 34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read() 36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read() 38 bank &= 0x3; in vsc8584_macsec_phy_read() 40 bank = 0; in vsc8584_macsec_phy_read() 45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read() 62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument 72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write() 74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) in vsc8584_macsec_phy_write() 75 bank &= 0x3; in vsc8584_macsec_phy_write() [all …]
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/linux-6.6.21/drivers/bus/ |
D | uniphier-system-bus.c | 35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member 39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument 45 bank, addr, paddr, size); in uniphier_system_bus_add_bank() 47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank() 48 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank() 52 if (priv->bank[bank].base || priv->bank[bank].end) { in uniphier_system_bus_add_bank() 54 "range for bank %d has already been specified\n", bank); in uniphier_system_bus_add_bank() 86 priv->bank[bank].base = paddr; in uniphier_system_bus_add_bank() 87 priv->bank[bank].end = end; in uniphier_system_bus_add_bank() 90 bank, priv->bank[bank].base, priv->bank[bank].end); in uniphier_system_bus_add_bank() [all …]
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/linux-6.6.21/drivers/leds/ |
D | leds-tca6507.c | 162 struct bank { struct 167 } bank[3]; member 178 int bank; /* Bank used, or -1 */ member 281 static void set_code(struct tca6507_chip *tca, int reg, int bank, int new) in set_code() argument 285 if (bank) { in set_code() 298 static void set_level(struct tca6507_chip *tca, int bank, int level) in set_level() argument 300 switch (bank) { in set_level() 303 set_code(tca, TCA6507_MAX_INTENSITY, bank, level); in set_level() 309 tca->bank[bank].level = level; in set_level() 313 static void set_times(struct tca6507_chip *tca, int bank) in set_times() argument [all …]
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/linux-6.6.21/drivers/pinctrl/ |
D | pinctrl-rockchip.c | 657 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument 660 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux() 667 if (data->num == bank->bank_num && in rockchip_get_recalced_mux() 1017 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument 1020 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route() 1027 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route() 1042 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument 1044 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux() 1055 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux() 1060 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux() [all …]
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/linux-6.6.21/sound/pci/au88x0/ |
D | au88x0_wt.h | 21 #define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */ argument 22 #define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */ argument 23 #define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */ argument 24 #define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */ argument 25 #define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */ argument 26 #define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */ argument
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/linux-6.6.21/arch/arm/boot/dts/samsung/ |
D | exynos5410-pinctrl.dtsi | 12 gpa0: gpa0-gpio-bank { 20 gpa1: gpa1-gpio-bank { 28 gpa2: gpa2-gpio-bank { 36 gpb0: gpb0-gpio-bank { 44 gpb1: gpb1-gpio-bank { 52 gpb2: gpb2-gpio-bank { 60 gpb3: gpb3-gpio-bank { 68 gpc0: gpc0-gpio-bank { 76 gpc3: gpc3-gpio-bank { 84 gpc1: gpc1-gpio-bank { [all …]
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/linux-6.6.21/drivers/pinctrl/sunxi/ |
D | pinctrl-sunxi.h | 32 #define SUNXI_PINCTRL_PIN(bank, pin) \ argument 33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin) 226 static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank) in sunxi_irq_hw_bank_num() argument 229 return bank; in sunxi_irq_hw_bank_num() 231 return desc->irq_bank_map[bank]; in sunxi_irq_hw_bank_num() 237 u8 bank = irq / IRQ_PER_BANK; in sunxi_irq_cfg_reg() local 241 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg; in sunxi_irq_cfg_reg() 250 static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank) in sunxi_irq_ctrl_reg_from_bank() argument 252 return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE; in sunxi_irq_ctrl_reg_from_bank() 258 u8 bank = irq / IRQ_PER_BANK; in sunxi_irq_ctrl_reg() local [all …]
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