Searched refs:array_mode (Results 1 – 9 of 9) sorted by relevance
| /linux-6.6.21/drivers/gpu/drm/radeon/ |
| D | r600_cs.c | 239 int array_mode; member
261 switch (values->array_mode) { in r600_get_array_mode_alignment()
357 unsigned array_mode; in r600_cs_track_validate_cb() local
376 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]); in r600_cs_track_validate_cb()
379 array_check.array_mode = array_mode; in r600_cs_track_validate_cb()
392 switch (array_mode) { in r600_cs_track_validate_cb()
413 __func__, __LINE__, pitch, pitch_align, array_mode); in r600_cs_track_validate_cb()
418 __func__, __LINE__, height, height_align, array_mode); in r600_cs_track_validate_cb()
423 base_offset, base_align, array_mode); in r600_cs_track_validate_cb()
430 switch (array_mode) { in r600_cs_track_validate_cb()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_debug.c | 162 plane_state->tiling_info.gfx8.array_mode, in pre_surface_trace()
251 update->plane_info->tiling_info.gfx8.array_mode, in update_surface_trace()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_mem_input.c | 103 switch (tiling_info->gfx8.array_mode) { in get_mi_tiling()
458 GRPH_ARRAY_MODE, info->gfx8.array_mode, in program_tiling()
475 GRPH_ARRAY_MODE, info->gfx8.array_mode, in program_tiling()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_mem_input_v.c | 193 set_reg_field_value(value, info->gfx8.array_mode, in program_tiling()
546 switch (tiling_info->gfx8.array_mode) { in get_dvmm_hw_setting()
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| D | dce110_hw_sequencer.c | 2039 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in should_enable_fbc()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_hw_sequencer.c | 105 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in dce60_should_enable_fbc()
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| /linux-6.6.21/drivers/gpu/drm/amd/display/dc/ |
| D | dc_hw_types.h | 384 enum array_mode_values array_mode; member
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| /linux-6.6.21/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_plane.c | 195 tiling_info->gfx8.array_mode = in fill_gfx8_tiling_info_from_flags()
205 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; in fill_gfx8_tiling_info_from_flags()
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| D | amdgpu_dm.c | 6539 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; in dm_validate_stream_and_context()
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