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/linux-6.6.21/drivers/clk/sunxi-ng/
Dccu_mux.h32 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ argument
35 .width = _width, \
39 #define _SUNXI_CCU_MUX(_shift, _width) \ argument
40 _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
50 _reg, _shift, _width, _gate, \ argument
54 .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
67 _width, _gate, _flags) \ argument
70 _width, _gate, _flags, \
74 _reg, _shift, _width, _gate, \ argument
78 _width, _gate, _flags, 0)
[all …]
Dccu_div.h43 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ argument
46 .width = _width, \
51 #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \ argument
52 _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
54 #define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \ argument
57 .width = _width, \
63 #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \ argument
64 _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
66 #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ argument
67 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
[all …]
Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
23 .width = _width, \
26 #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \ argument
27 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, 0)
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
32 #define _SUNXI_CCU_MULT(_shift, _width) \ argument
33 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, 1, 0)
Dccu_phase.h20 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
23 .width = _width, \
/linux-6.6.21/drivers/clk/sprd/
Dmux.h32 #define _SPRD_MUX_CLK(_shift, _width, _table) \ argument
35 .width = _width, \
40 _reg, _shift, _width, _flags, _fn) \ argument
42 .mux = _SPRD_MUX_CLK(_shift, _width, _table), \
52 _reg, _shift, _width, _flags) \ argument
54 _reg, _shift, _width, _flags, \
58 _shift, _width, _flags) \ argument
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \ argument
65 _reg, _shift, _width, _flags, \
[all …]
Ddiv.h27 #define _SPRD_DIV_CLK(_shift, _width) \ argument
30 .width = _width, \
39 _shift, _width, _flags, _fn) \ argument
41 .div = _SPRD_DIV_CLK(_shift, _width), \
51 _shift, _width, _flags) \ argument
53 _shift, _width, _flags, CLK_HW_INIT)
56 _shift, _width, _flags) \ argument
58 _shift, _width, _flags, CLK_HW_INIT_HW)
/linux-6.6.21/drivers/clk/actions/
Dowl-pll.h42 _width, _min_mul, _max_mul, _delay, _table) \ argument
48 .width = _width, \
56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
59 _width, _min_mul, _max_mul, \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
74 _width, _min_mul, _max_mul, \
85 _shift, _width, _min_mul, _max_mul, _delay, _table, \ argument
89 _width, _min_mul, _max_mul, \
Dowl-mux.h27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument
31 .width = _width, \
35 _shift, _width, _flags) \ argument
37 .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \
Dowl-divider.h29 #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ argument
33 .width = _width, \
39 _shift, _width, _table, _div_flags, _flags) \ argument
41 .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \
Dowl-factor.h35 #define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table) \ argument
39 .width = _width, \
45 _shift, _width, _table, _fct_flags, _flags) \ argument
48 _width, _fct_flags, _table), \
/linux-6.6.21/drivers/clk/mediatek/
Dclk-mtk.h113 _width, _gate, _flags, _muxflags) { \ argument
118 .mux_width = _width, \
132 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
135 _shift, _width, _gate, _flags, 0)
141 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
142 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
145 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
147 _shift, _width, CLK_SET_RATE_PARENT)
149 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
154 .mux_width = _width, \
[all …]
Dclk-mux.h41 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
50 .mux_width = _width, \
63 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
66 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
71 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
75 _width, _gate, _upd_ofs, _upd, \
79 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
82 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
Dclk-mt6795-topckgen.c21 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
23 (_reg + 0x4), (_reg + 0x8), _shift, _width, \
26 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
27 TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
Dclk-mt8173-topckgen.c22 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
24 (_reg + 0x4), (_reg + 0x8), _shift, _width, \
27 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
28 TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
Dclk-mt8167-apmixedsys.c77 #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ argument
83 .div_width = _width, \
/linux-6.6.21/drivers/clk/x86/
Dclk-cgu.h204 _shift, _width, _cf, _v) \ argument
214 .mux_width = _width, \
219 #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \ argument
233 .div_width = _width, \
260 _shift, _width, _cf, _freq, _v) \ argument
273 .div_width = _width, \
280 _shift, _width, _cf, _v, _m, _d) \ argument
293 .div_width = _width, \
/linux-6.6.21/drivers/clk/pistachio/
Dclk.h59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
63 .width = _width, \
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
73 .width = _width, \
/linux-6.6.21/drivers/dma/fsl-dpaa2-qdma/
Ddpdmai.h45 #define MAKE_UMASK64(_width) \ argument
46 ((u64)((_width) < 64 ? ((u64)1 << (_width)) - 1 : (u64)-1))
/linux-6.6.21/drivers/clk/bcm/
Dclk-kona.h291 #define DIVIDER(_offset, _shift, _width) \ argument
295 .u.s.width = (_width), \
301 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
305 .u.s.width = (_width), \
342 #define SELECTOR(_offset, _shift, _width) \ argument
346 .width = (_width), \
/linux-6.6.21/drivers/pinctrl/berlin/
Dberlin.h37 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
41 .bit_width = _width, \
/linux-6.6.21/drivers/clk/microchip/
Dclk-mpfs-ccc.c101 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ argument
104 .width = _width, \
124 #define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \ argument
127 .divider.width = _width, \
Dclk-mpfs.c172 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ argument
175 .width = _width, \
211 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ argument
214 .cfg.width = _width, \
/linux-6.6.21/drivers/net/ethernet/amd/xgbe/
Dxgbe-common.h1448 #define GET_BITS(_var, _index, _width) \ argument
1449 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1451 #define SET_BITS(_var, _index, _width, _val) \ argument
1453 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
1454 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1457 #define GET_BITS_LE(_var, _index, _width) \ argument
1458 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1460 #define SET_BITS_LE(_var, _index, _width, _val) \ argument
1462 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \
1464 ((0x1 << (_width)) - 1)) << (_index))); \
/linux-6.6.21/drivers/clk/meson/
Dclk-phase.c13 #define phase_step(_width) (360 / (1 << (_width))) argument
/linux-6.6.21/include/uapi/linux/
Dv4l2-dv-timings.h16 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ argument
17 { .bt = { _width , ## args } }
19 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ argument
20 .bt = { _width , ## args }

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