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Searched refs:_pwr_reg (Results 1 – 21 of 21) sorted by relevance

/linux-6.6.21/drivers/clk/mediatek/
Dclk-mt7986-apmixed.c23 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
27 .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
36 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
38 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
Dclk-mt7981-apmixed.c25 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
29 .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
38 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
40 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
Dclk-mt8516-apmixedsys.c23 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
29 .pwr_reg = _pwr_reg, \
43 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
46 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
Dclk-mt8167-apmixedsys.c22 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
28 .pwr_reg = _pwr_reg, \
42 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
45 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
Dclk-mt7622-apmixedsys.c20 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ argument
26 .pwr_reg = _pwr_reg, \
41 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
44 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
Dclk-mt2712-apmixedsys.c21 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
28 .pwr_reg = _pwr_reg, \
44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
47 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
Dclk-mt8365-apmixedsys.c19 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
26 .pwr_reg = _pwr_reg, \
45 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
49 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
Dclk-mt8183-apmixedsys.c54 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
62 .pwr_reg = _pwr_reg, \
81 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
86 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
Dclk-mt8173-apmixedsys.c24 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
30 .pwr_reg = _pwr_reg, \
44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
47 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
Dclk-mt8192-apmixedsys.c35 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
43 .pwr_reg = _pwr_reg, \
63 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
67 PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
Dclk-mt8135-apmixedsys.c20 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg,… argument
24 .pwr_reg = _pwr_reg, \
Dclk-mt8195-apusys_pll.c28 #define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) { \ argument
32 .pwr_reg = _pwr_reg, \
Dclk-mt8188-apmixedsys.c32 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
40 .pwr_reg = _pwr_reg, \
Dclk-mt7629.c23 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
29 .pwr_reg = _pwr_reg, \
44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
47 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
Dclk-mt8186-apmixedsys.c19 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
26 .pwr_reg = _pwr_reg, \
Dclk-mt6797.c599 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
605 .pwr_reg = _pwr_reg, \
619 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
622 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
Dclk-mt6795-apmixedsys.c26 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
31 .pwr_reg = _pwr_reg, \
Dclk-mt8195-apmixedsys.c33 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
41 .pwr_reg = _pwr_reg, \
Dclk-mt6765.c671 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
677 .pwr_reg = _pwr_reg, \
695 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
699 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
Dclk-mt6779.c1145 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
1153 .pwr_reg = _pwr_reg, \
1172 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
1177 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
Dclk-mt2701.c921 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
926 .pwr_reg = _pwr_reg, \