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/linux-6.6.21/drivers/clk/sprd/
Dgate.h32 _sc_offset, _enable_mask, _flags, \ argument
43 _ops, _flags), \
48 _sc_offset, _enable_mask, _flags, \ argument
51 _sc_offset, _enable_mask, _flags, \
55 _enable_mask, _flags, _gate_flags, _ops) \ argument
57 _sc_offset, _enable_mask, _flags, \
61 _enable_mask, _flags, _gate_flags) \ argument
63 _enable_mask, _flags, _gate_flags, \
67 _enable_mask, _flags, _gate_flags) \ argument
69 _enable_mask, _flags, _gate_flags, \
[all …]
Dcomposite.h23 _flags, _fn) \ argument
31 &sprd_comp_ops, _flags), \
36 _mshift, _mwidth, _dshift, _dwidth, _flags) \ argument
39 _flags, CLK_HW_INIT_PARENTS)
42 _mwidth, _dshift, _dwidth, _flags) \ argument
44 _mshift, _mwidth, _dshift, _dwidth, _flags)
48 _dwidth, _flags) \ argument
51 _flags, CLK_HW_INIT_PARENTS_DATA)
54 _mwidth, _dshift, _dwidth, _flags) \ argument
57 _flags)
Dmux.h40 _reg, _shift, _width, _flags, _fn) \ argument
47 &sprd_mux_ops, _flags), \
52 _reg, _shift, _width, _flags) \ argument
54 _reg, _shift, _width, _flags, \
58 _shift, _width, _flags) \ argument
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \ argument
65 _reg, _shift, _width, _flags, \
69 _shift, _width, _flags) \ argument
71 _reg, _shift, _width, _flags)
Ddiv.h39 _shift, _width, _flags, _fn) \ argument
46 &sprd_div_ops, _flags), \
51 _shift, _width, _flags) \ argument
53 _shift, _width, _flags, CLK_HW_INIT)
56 _shift, _width, _flags) \ argument
58 _shift, _width, _flags, CLK_HW_INIT_HW)
/linux-6.6.21/drivers/clk/sunxi-ng/
Dccu_div.h43 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ argument
47 .flags = _flags, \
54 #define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \ argument
58 .flags = _flags, \
63 #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \ argument
64 _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
66 #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ argument
67 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
89 _table, _gate, _flags) \ argument
99 _flags), \
[all …]
Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
27 _flags), \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
39 _flags), \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
51 _flags), \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
67 _flags), \
72 _gate, _prediv, _flags) \ argument
82 _flags), \
[all …]
Dccu_mux.h51 _flags, _features) \ argument
60 _flags), \
67 _width, _gate, _flags) \ argument
70 _width, _gate, _flags, \
75 _flags) \ argument
78 _width, _gate, _flags, 0)
81 _shift, _width, _gate, _flags) \ argument
84 _flags)
87 _flags) \ argument
89 _reg, _shift, _width, 0, _flags)
[all …]
Dccu_mp.h38 _gate, _postdiv, _flags) \ argument
51 _flags), \
59 _gate, _flags) \ argument
70 _flags), \
78 _flags) \ argument
83 0, _flags)
89 _gate, _flags) \ argument
100 _flags), \
108 _flags) \ argument
113 0, _flags)
[all …]
Dccu_nm.h43 _gate, _lock, _flags) \ argument
57 _flags), \
66 _gate, _lock, _flags) \ argument
81 _flags), \
91 _gate, _lock, _flags) \ argument
107 _flags), \
119 _gate, _lock, _flags, \ argument
137 _flags), \
149 _gate, _lock, _flags) \ argument
158 _gate, _lock, _flags, \
[all …]
Dccu_nkm.h39 _gate, _lock, _flags) \ argument
52 _flags), \
60 _gate, _lock, _flags) \ argument
72 _flags), \
/linux-6.6.21/drivers/clk/actions/
Dowl-composite.h38 _mux, _gate, _div, _flags) \ argument
48 _flags), \
53 _gate, _div, _flags) \ argument
62 _flags), \
67 _mux, _gate, _factor, _flags) \ argument
77 _flags), \
82 _gate, _mul, _div, _flags) \ argument
93 _flags), \
98 _mux, _gate, _flags) \ argument
107 _flags), \
Dowl-pll.h56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
66 _flags), \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
80 _flags), \
86 _flags) \ argument
95 _flags), \
Dowl-gate.h35 _bit_idx, _gate_flags, _flags) \ argument
43 _flags), \
48 _bit_idx, _gate_flags, _flags) \ argument
55 _flags), \
/linux-6.6.21/drivers/gpu/drm/amd/pm/inc/
Damdgpu_pm.h62 #define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \ argument
64 .flags = _flags, \
67 #define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...) \ argument
70 _flags, ##__VA_ARGS__)
72 #define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...) \ argument
74 _flags, ##__VA_ARGS__)
76 #define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...) \ argument
79 _flags, ##__VA_ARGS__)
/linux-6.6.21/drivers/staging/media/atomisp/include/media/
Dlm3554.h29 _default_value, _flags) \ argument
38 .flags = (_flags),\
41 _default_value, _flags) \ argument
50 .flags = (_flags),\
55 _default_value, _flags, \ argument
60 _default_value, _flags), \
66 _default_value, _flags, \ argument
70 _default_value, _flags), \
/linux-6.6.21/include/linux/
Dtimer.h76 #define __TIMER_INITIALIZER(_function, _flags) { \ argument
79 .flags = (_flags), \
112 #define __init_timer(_timer, _fn, _flags) \ argument
115 init_timer_key((_timer), (_fn), (_flags), #_timer, &__key);\
118 #define __init_timer_on_stack(_timer, _fn, _flags) \ argument
121 init_timer_on_stack_key((_timer), (_fn), (_flags), \
125 #define __init_timer(_timer, _fn, _flags) \ argument
126 init_timer_key((_timer), (_fn), (_flags), NULL, NULL)
127 #define __init_timer_on_stack(_timer, _fn, _flags) \ argument
128 init_timer_on_stack_key((_timer), (_fn), (_flags), NULL, NULL)
Dirqflags.h103 # define lockdep_irq_work_enter(_flags) \ argument
105 if (!((_flags) & IRQ_WORK_HARD_IRQ)) \
108 # define lockdep_irq_work_exit(_flags) \ argument
110 if (!((_flags) & IRQ_WORK_HARD_IRQ)) \
261 unsigned long _flags; \
262 raw_local_save_flags(_flags); \
263 raw_irqs_disabled_flags(_flags); \
Dsh_clk.h117 #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \ argument
123 .flags = _flags, \
151 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ argument
158 .flags = _flags, \
175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
180 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
188 #define SH_CLK_DIV6(_parent, _reg, _flags) \ argument
194 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
/linux-6.6.21/drivers/clk/starfive/
Dclk-starfive-jh71x0.h32 #define JH71X0_GATE(_idx, _name, _flags, _parent) \ argument
35 .flags = CLK_SET_RATE_PARENT | (_flags), \
48 #define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \ argument
51 .flags = _flags, \
72 #define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \ argument
75 .flags = _flags, \
89 #define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \ argument
92 .flags = _flags, \
/linux-6.6.21/drivers/net/ethernet/fungible/funcore/
Dfun_hci.h39 #define FUN_ADMIN_REQ_COMMON_INIT(_op, _len8, _flags, _suboff8, _cid) \ argument
41 .op = (_op), .len8 = (_len8), .flags = cpu_to_be16(_flags), \
157 #define FUN_ADMIN_SIMPLE_SUBOP_INIT(_subop, _flags, _data) \ argument
159 .subop = (_subop), .flags = cpu_to_be16(_flags), \
254 _subop, _flags, _id, _epsqid, _entry_size_log2, _nentries, _address, \ argument
259 .subop = (_subop), .flags = cpu_to_be16(_flags), \
274 #define FUN_ADMIN_EPCQ_MODIFY_REQ_INIT(_subop, _flags, _id, _headroom) \ argument
276 .subop = (_subop), .flags = cpu_to_be16(_flags), \
329 _subop, _flags, _id, _epcqid, _entry_size_log2, _nentries, _address, \ argument
334 .subop = (_subop), .flags = cpu_to_be16(_flags), \
[all …]
/linux-6.6.21/include/linux/gpio/
Dmachine.h69 #define GPIO_LOOKUP_SINGLE(_name, _dev_id, _key, _chip_hwnum, _con_id, _flags) \ argument
73 GPIO_LOOKUP(_key, _chip_hwnum, _con_id, _flags), \
81 #define GPIO_LOOKUP(_key, _chip_hwnum, _con_id, _flags) \ argument
82 GPIO_LOOKUP_IDX(_key, _chip_hwnum, _con_id, 0, _flags)
89 #define GPIO_LOOKUP_IDX(_key, _chip_hwnum, _con_id, _idx, _flags) \ argument
95 .flags = _flags, \
/linux-6.6.21/lib/
Dtest_dynamic_debug.c42 #define DD_SYS_WRAP(_model, _flags) \ argument
44 static struct ddebug_class_param _flags##_model = { \
46 .flags = #_flags, \
49 module_param_cb(_flags##_##_model, &param_ops_dyndbg_classes, &_flags##_model, 0600)
/linux-6.6.21/drivers/clk/mediatek/
Dclk-mt8183-apmixedsys.c24 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
26 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
54 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
64 .flags = _flags, \
81 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
86 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
Dclk-mt7986-apmixed.c23 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
28 .en_mask = _en_mask, .flags = _flags, \
36 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
38 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
Dclk-mt7981-apmixed.c25 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
30 .en_mask = _en_mask, .flags = _flags, \
38 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
40 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \

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