| /linux-6.6.21/drivers/gpu/drm/amd/amdgpu/ |
| D | vce_v3_0.c | 165 WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0); in vce_v3_0_override_vce_clock_gating()
249 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v3_0_firmware_loaded()
251 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v3_0_firmware_loaded()
303 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1); in vce_v3_0_start()
308 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1); in vce_v3_0_start()
310 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v3_0_start()
316 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0); in vce_v3_0_start()
345 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0); in vce_v3_0_stop()
348 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v3_0_stop()
600 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1); in vce_v3_0_mc_resume()
[all …]
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| D | vce_v2_0.c | 201 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1); in vce_v2_0_mc_resume()
257 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1); in vce_v2_0_start()
258 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v2_0_start()
260 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v2_0_start()
541 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1); in vce_v2_0_soft_reset()
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| D | gfx_v8_0.c | 3737 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF); in gfx_v8_0_constants_init()
3954 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1); in gfx_v8_0_init_save_restore_list()
3993 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1); in gfx_v8_0_enable_save_restore_machine()
4000 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60); in gfx_v8_0_init_power_gating()
4008 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3); in gfx_v8_0_init_power_gating()
4009 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0); in gfx_v8_0_init_power_gating()
4016 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_up()
4022 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_down()
4027 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1); in cz_enable_cp_power_gating()
4053 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v8_0_rlc_stop()
[all …]
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| D | uvd_v6_0.c | 738 WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0); in uvd_v6_0_start()
741 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1); in uvd_v6_0_start()
757 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0); in uvd_v6_0_start()
792 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0); in uvd_v6_0_start()
812 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1); in uvd_v6_0_start()
814 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0); in uvd_v6_0_start()
859 WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0); in uvd_v6_0_start()
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| D | vce_v4_0.c | 748 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
753 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);
758 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
940 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i);
959 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
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| D | gfx_v6_0.c | 2391 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v6_0_enable_lbpw()
2460 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v6_0_rlc_reset()
2462 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v6_0_rlc_reset()
2735 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); in gfx_v6_0_enable_gfx_cgpg()
2736 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); in gfx_v6_0_enable_gfx_cgpg()
2738 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); in gfx_v6_0_enable_gfx_cgpg()
2788 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); in gfx_v6_0_init_gfx_cgpg()
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| D | amdgpu_amdkfd_gfx_v8.c | 408 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0); in kgd_hqd_destroy()
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| D | uvd_v3_1.c | 211 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v3_1_set_dcm()
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| D | uvd_v4_2.c | 635 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v4_2_set_dcm()
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| D | amdgpu.h | 1234 #define WREG32_FIELD(reg, field, val) \ macro
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| /linux-6.6.21/drivers/accel/habanalabs/common/ |
| D | habanalabs.h | 2550 #define WREG32_FIELD(reg, offset, field, val) \ macro
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| /linux-6.6.21/drivers/accel/habanalabs/goya/ |
| D | goya.c | 1804 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset, in goya_init_golden_registers()
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| /linux-6.6.21/drivers/accel/habanalabs/gaudi/ |
| D | gaudi.c | 2530 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, tpc_offset, in gaudi_init_golden_registers()
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