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Searched refs:WDT (Results 1 – 25 of 57) sorted by relevance

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/linux-6.6.21/Documentation/devicetree/bindings/watchdog/
Dimgpdc-wdt.txt1 *ImgTec PowerDown Controller (PDC) Watchdog Timer (WDT)
5 - reg : Should contain WDT registers location and length
9 - interrupts : Should contain WDT interrupt
Dlpc18xx-wdt.txt1 * NXP LPC18xx Watchdog Timer (WDT)
5 - reg: Should contain WDT registers location and length
9 - interrupts: Should contain WDT interrupt
Dxlnx,xps-timebase-wdt.yaml14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
16 the timeout interval, an interrupt is generated and the WDT state
19 expiration of the timeout interval, a WDT reset is generated.
Dlinux,wdt-gpio.yaml18 description: gpio connection to WDT reset pin
25 Either a high-to-low or a low-to-high transition clears the WDT counter.
30 Low or high level starts counting WDT timeout, the opposite level
31 disables the WDT.
Domap-wdt.txt1 TI Watchdog Timer (WDT) Controller for OMAP
5 - ti,hwmods : Name of the hwmod associated to the WDT
Ddavinci-wdt.txt1 Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
5 - reg : Should contain WDT registers location and length
Drealtek,otto-wdt.yaml17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
20 During this phase, pinging the WDT has no effect, and a reset is
21 unavoidable, unless the WDT is disabled.
Dqca-ar7130-wdt.txt1 * Qualcomm Atheros AR7130 Watchdog Timer (WDT) Controller
/linux-6.6.21/arch/sh/kernel/cpu/sh4/
Dsetup-sh4-202.c89 HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT, enumerator
100 INTC_VECT(WDT, 0x560),
105 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
Dsetup-sh7750.c185 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF, enumerator
201 INTC_VECT(WDT, 0x560),
207 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
Dsetup-sh7760.c37 WDT, REF, enumerator
74 INTC_VECT(WDT, 0x560),
105 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
/linux-6.6.21/arch/sh/kernel/cpu/sh3/
Dsetup-sh7705.c31 RTC, WDT, REF_RCMI, enumerator
51 INTC_VECT(WDT, 0x560),
57 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
Dsetup-sh7710.c28 RTC, WDT, REF, enumerator
53 INTC_VECT(WDT, 0x560),
59 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
Dsetup-sh770x.c32 RTC, WDT, REF, enumerator
42 INTC_VECT(WDT, 0x560),
69 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
Dsetup-sh7720.c224 WDT, REF_RCMI, SIM, enumerator
243 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
268 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
/linux-6.6.21/arch/sh/kernel/cpu/sh2/
Dsetup-sh7619.c22 WDT, EDMAC, CMT0, CMT1, enumerator
34 INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
51 { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
/linux-6.6.21/Documentation/watchdog/
Dwatchdog-parameters.rst29 Acquire WDT 'stop' io port (default 0x43)
31 Acquire WDT 'start' io port (default 0x443)
40 Advantech WDT 'stop' io port (default 0x443)
42 Advantech WDT 'start' io port (default 0x443)
179 Eurotech WDT io port (default=0x3f0)
181 Eurotech WDT irq (default=10)
183 Eurotech WDT event type (default is `int`)
391 pc87413 WDT I/O port (default: io).
484 SBC60xx WDT 'stop' io port (default 0x45)
486 SBC60xx WDT 'start' io port (default 0x443)
[all …]
Dwdt.rst2 WDT Watchdog Timer Interfaces For The Linux Operating System
57 The external event interfaces on the WDT boards are not currently supported.
/linux-6.6.21/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7763.c240 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, enumerator
256 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
306 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
318 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
Dsetup-sh7780.c304 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, enumerator
317 INTC_VECT(WDT, 0x560),
360 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
367 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
Dsetup-sh7785.c377 WDT, TMU0, TMU1, TMU2, TMU2_TICPI, enumerator
393 INTC_VECT(WDT, 0x560),
455 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
467 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
/linux-6.6.21/arch/sh/kernel/cpu/sh2a/
Dsetup-sh7206.c30 CMT0, CMT1, BSC, WDT, enumerator
61 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
112 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
Dsetup-sh7201.c28 RTC, WDT, enumerator
91 INTC_IRQ(WDT, 156),
159 { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
Dsetup-sh7203.c22 USB, LCDC, CMT0, CMT1, BSC, WDT, enumerator
63 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
144 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
/linux-6.6.21/Documentation/devicetree/bindings/power/reset/
Dkeystone-reset.txt29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
30 to WDT driver, it's just needed to enable a SoC related

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