/linux-6.6.21/Documentation/devicetree/bindings/hwmon/ |
D | ltc2990.txt | 13 0: V1, V2, TR2 14 1: V1-V2, TR2 15 2: V1-V2, V3, V4 19 6: V1-V2, V3-V4 20 7: V1, V2, V3, V4 26 1: TR1, V1 or V1-V2 only per mode 35 lltc,meas-mode = <7 3>; /* V1, V2, V3, V4 */
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/linux-6.6.21/arch/powerpc/lib/ |
D | xor_vmx.c | 44 #define XOR(V1, V2) \ argument 46 V1##_0 = vec_xor(V1##_0, V2##_0); \ 47 V1##_1 = vec_xor(V1##_1, V2##_1); \ 48 V1##_2 = vec_xor(V1##_2, V2##_2); \ 49 V1##_3 = vec_xor(V1##_3, V2##_3); \
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/linux-6.6.21/arch/arm64/boot/dts/marvell/ |
D | armada-3720-db.dts | 72 /* Gigabit module on CON19(V2.0)/CON21(V1.4) */ 81 /* Gigabit module on CON18(V2.0)/CON20(V1.4) */ 129 /* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */ 151 /* SD slot module on CON14(V2.0)/CON15(V1.4) */ 195 * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through 196 * an FTDI (also on CON24(V2.0)/CON26(V1.4)). 204 /* CON26(V2.0)/CON28(V1.4) */ 211 /* CON27(V2.0)/CON29(V1.4) */ 216 /* CON29(V2.0)/CON31(V1.4) */
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/linux-6.6.21/scripts/ |
D | Lindent | 10 V1=`echo $RES | cut -d'.' -f1` 14 if [ $V1 -gt 2 ]; then 16 elif [ $V1 -eq 2 ]; then
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/linux-6.6.21/Documentation/arch/arm/ |
D | sunxi.rst | 65 http://dl.linux-sunxi.org/A23/A23%20Datasheet%20V1.0%2020130830.pdf 69 http://dl.linux-sunxi.org/A23/A23%20User%20Manual%20V1.0%2020130830.pdf 76 … http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf 80 …http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20user%20manual%20V1.1%2020130630.pdf 86 … http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20datasheet%20V1.3%2020131106.pdf 90 …http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20User%20Manual%20%20V1.0%20201303…
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/linux-6.6.21/arch/mips/kvm/ |
D | entry.c | 26 #define V1 3 macro 231 kvm_mips_build_save_scratch(&p, V1, K1); in kvm_mips_build_vcpu_run() 329 uasm_i_addiu(&p, V1, ZERO, 1); in kvm_mips_build_enter_guest() 331 uasm_i_ins(&p, K0, V1, MIPS_GCTL0_GM_SHIFT, 1); in kvm_mips_build_enter_guest() 660 uasm_i_and(&p, V1, V0, AT); in kvm_mips_build_exit() 661 uasm_il_beqz(&p, &r, V1, label_fpu_1); in kvm_mips_build_exit() 852 uasm_i_mfc0(&p, V1, C0_STATUS); in kvm_mips_build_ret_to_guest() 854 uasm_i_or(&p, K0, V1, AT); in kvm_mips_build_ret_to_guest() 860 uasm_i_ori(&p, V1, V1, ST0_EXL | KSU_USER | ST0_IE); in kvm_mips_build_ret_to_guest() 862 uasm_i_and(&p, V1, V1, AT); in kvm_mips_build_ret_to_guest() [all …]
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/linux-6.6.21/arch/arm64/boot/dts/freescale/ |
D | imx8qm-apalis-v1.1-ixora-v1.1.dts | 12 model = "Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.1 Carrier Board";
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D | imx8qm-apalis-v1.1-ixora-v1.2.dts | 12 model = "Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.2 Carrier Board";
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D | imx8qm-apalis.dtsi | 19 * Apalis iMX8QM V1.0 has PHY KSZ9031. the Micrel PHY driver 327 * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates 336 * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates
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D | imx8mp-verdin-yavia.dtsi | 9 /* Carrier Board Supply +V1.8 */ 14 regulator-name = "+V1.8_SW";
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D | imx8mm-emtop-baseboard.dts | 11 model = "Emtop Embedded Solutions i.MX8M Mini Baseboard V1";
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D | imx8qm-apalis-v1.1.dtsi | 11 model = "Toradex Apalis iMX8QM V1.1";
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D | imx8qm-apalis-v1.1-eval.dts | 12 model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board";
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D | imx8qm-apalis-ixora-v1.1.dts | 12 model = "Toradex Apalis iMX8QM/QP on Apalis Ixora V1.1 Carrier Board";
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/linux-6.6.21/arch/arm/boot/dts/nvidia/ |
D | tegra30-colibri.dtsi | 6 * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B 771 regulator-name = "+V1.35_VDDIO_DDR"; 780 regulator-name = "+V1.0_VDD_CPU"; 792 regulator-name = "+V1.8"; 802 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN 815 regulator-name = "+V1.2_VDD_RTC"; 833 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V 838 regulator-name = "+V1.05_AVDD_PLLE"; 844 regulator-name = "+V1.2_AVDD_PLL"; 851 regulator-name = "+V1.0_VDD_DDR_HS"; [all …]
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D | tegra30-apalis-v1.1.dtsi | 6 * Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B; 7 * 2GB: V1.1A, V1.1B 895 regulator-name = "+V1.35_VDDIO_DDR"; 902 regulator-name = "+V1.05"; 908 regulator-name = "+V1.0_VDD_CPU"; 915 regulator-name = "+V1.8"; 945 regulator-name = "+V1.2_CSI"; 951 regulator-name = "+V1.2_VDD_RTC"; 969 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V 974 regulator-name = "+V1.05_AVDD_PLLE"; [all …]
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D | tegra30-apalis.dtsi | 6 * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E 887 regulator-name = "+V1.35_VDDIO_DDR"; 894 regulator-name = "+V1.05"; 900 regulator-name = "+V1.0_VDD_CPU"; 907 regulator-name = "+V1.8"; 928 regulator-name = "+V1.2_CSI"; 934 regulator-name = "+V1.2_VDD_RTC"; 952 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V 957 regulator-name = "+V1.05_AVDD_PLLE"; 963 regulator-name = "+V1.2_AVDD_PLL"; [all …]
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/linux-6.6.21/arch/arm64/boot/dts/renesas/ |
D | r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts | 19 * On RZ/G2M SoC LSI V1.3 CSI40 supports only 4 lane mode. 20 * HiHope RZ/G2M Rev.4.0 board is based on LSI V1.3 so disable csi40 and
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/linux-6.6.21/Documentation/gpu/amdgpu/ |
D | apu-asic-info-table.csv | 3 Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0,… 5 Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.…
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/linux-6.6.21/lib/ |
D | test_dynamic_debug.c | 85 enum cat_level_num { V0 = 14, V1, V2, V3, V4, V5, V6, V7 }; enumerator 125 prdbg(V1); in do_levels()
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/linux-6.6.21/arch/arm/boot/dts/broadcom/ |
D | bcm4708-netgear-r6250.dts | 3 * DTS for Netgear R6250 V1 17 model = "Netgear R6250 V1 (BCM4708)";
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/linux-6.6.21/scripts/dtc/ |
D | dtc-lexer.l | 10 %s V1 154 <V1>([0-9]+|0[xX][0-9a-fA-F]+)(U|L|UL|LL|ULL)? {
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/linux-6.6.21/arch/arm/mach-alpine/ |
D | Kconfig | 14 This enables support for the Annapurna Labs Alpine V1 boards.
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/linux-6.6.21/arch/riscv/boot/dts/starfive/ |
D | jh7100-starfive-visionfive-v1.dts | 12 model = "StarFive VisionFive V1";
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/linux-6.6.21/drivers/regulator/ |
D | pcap-regulator.c | 109 VREG_INFO(V1, PCAP_REG_VREG1, 1, 2, 18, 0), 226 VREG(V1), VREG(V2), VREG(V3), VREG(V4), VREG(V5), VREG(V6), VREG(V7),
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