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Searched refs:UVD_STATUS__IDLE (Results 1 – 7 of 7) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c874 if (status & UVD_STATUS__IDLE) in vcn_v1_0_start_spg_mode()
879 if (status & UVD_STATUS__IDLE) in vcn_v1_0_start_spg_mode()
1124 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode()
1343 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle()
1351 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v1_0_wait_for_idle()
1352 UVD_STATUS__IDLE); in vcn_v1_0_wait_for_idle()
Dvcn_v4_0_3.c1269 UVD_STATUS__IDLE, 0x7); in vcn_v4_0_3_stop()
1470 UVD_STATUS__IDLE); in vcn_v4_0_3_is_idle()
1490 UVD_STATUS__IDLE, UVD_STATUS__IDLE); in vcn_v4_0_3_wait_for_idle()
1515 regUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v4_0_3_set_clockgating_state()
Dvcn_v4_0.c1474 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v4_0_stop()
1879 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v4_0_is_idle()
1901 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v4_0_wait_for_idle()
1902 UVD_STATUS__IDLE); in vcn_v4_0_wait_for_idle()
1929 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v4_0_set_clockgating_state()
Damdgpu_vcn.h198 UVD_STATUS__IDLE = 0x2, enumerator
Dvcn_v3_0.c1537 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v3_0_stop()
2070 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v3_0_is_idle()
2085 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v3_0_wait_for_idle()
2086 UVD_STATUS__IDLE); in vcn_v3_0_wait_for_idle()
2106 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v3_0_set_clockgating_state()
Dvcn_v2_0.c1146 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop()
1282 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_0_is_idle()
1290 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_0_wait_for_idle()
1291 UVD_STATUS__IDLE); in vcn_v2_0_wait_for_idle()
Dvcn_v2_5.c1394 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop()
1737 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle()
1751 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_5_wait_for_idle()
1752 UVD_STATUS__IDLE); in vcn_v2_5_wait_for_idle()