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Searched refs:UVD_MPC_SET_MUX__SET_2_MASK (Results 1 – 13 of 13) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h639 #define UVD_MPC_SET_MUX__SET_2_MASK … macro
Duvd_3_1_sh_mask.h513 #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 macro
Duvd_4_0_sh_mask.h532 #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001c0L macro
Duvd_4_2_sh_mask.h517 #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 macro
Duvd_5_0_sh_mask.h549 #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 macro
Duvd_6_0_sh_mask.h551 #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1146 #define UVD_MPC_SET_MUX__SET_2_MASK … macro
Dvcn_2_5_sh_mask.h2887 #define UVD_MPC_SET_MUX__SET_2_MASK … macro
Dvcn_2_0_0_sh_mask.h2652 #define UVD_MPC_SET_MUX__SET_2_MASK … macro
Dvcn_2_6_0_sh_mask.h2879 #define UVD_MPC_SET_MUX__SET_2_MASK … macro
Dvcn_3_0_0_sh_mask.h3960 #define UVD_MPC_SET_MUX__SET_2_MASK … macro
Dvcn_4_0_0_sh_mask.h4210 #define UVD_MPC_SET_MUX__SET_2_MASK … macro
Dvcn_4_0_3_sh_mask.h4253 #define UVD_MPC_SET_MUX__SET_2_MASK … macro