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Searched refs:UVD_MPC_SET_MUXB0__VARB_0__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h616 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT … macro
Duvd_3_1_sh_mask.h494 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 macro
Duvd_4_0_sh_mask.h513 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x00000000 macro
Duvd_4_2_sh_mask.h498 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 macro
Duvd_5_0_sh_mask.h530 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 macro
Duvd_6_0_sh_mask.h532 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1123 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT … macro
Dvcn_2_5_sh_mask.h2864 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2629 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT … macro
Dvcn_2_6_0_sh_mask.h2856 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3937 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4187 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT … macro
Dvcn_4_0_3_sh_mask.h4230 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT … macro