Searched refs:UVD_MPC_SET_MUXA0__VARA_1__SHIFT (Results 1 – 19 of 19) sorted by relevance
599 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
480 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 macro
499 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x00000006 macro
484 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 macro
516 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 macro
518 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 macro
1106 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
2847 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
2612 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
2839 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
3920 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
4170 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
4213 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT … macro
775 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v4_0_3_start_dpg_mode()1101 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v4_0_3_start()
844 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_0_start_dpg_mode()977 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_0_start()
831 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v1_0_start_spg_mode()1014 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v1_0_start_dpg_mode()
963 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v4_0_start_dpg_mode()1102 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v4_0_start()
869 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_5_start_dpg_mode()1023 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v2_5_start()
992 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v3_0_start_dpg_mode()1156 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | in vcn_v3_0_start()