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Searched refs:UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK (Results 1 – 12 of 12) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c1227 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); in vcn_v1_0_pause_dpg_mode()
1242 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, in vcn_v1_0_pause_dpg_mode()
1243 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); in vcn_v1_0_pause_dpg_mode()
1288 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) in vcn_v1_0_pause_dpg_mode()
Dvcn_v2_0.c1213 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); in vcn_v2_0_pause_dpg_mode()
1227 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, in vcn_v2_0_pause_dpg_mode()
1228 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); in vcn_v2_0_pause_dpg_mode()
Dvcn_v4_0.c1554 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); in vcn_v4_0_pause_dpg_mode()
1567 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, in vcn_v4_0_pause_dpg_mode()
1568 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); in vcn_v4_0_pause_dpg_mode()
Dvcn_v2_5.c1460 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); in vcn_v2_5_pause_dpg_mode()
1475 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, in vcn_v2_5_pause_dpg_mode()
1476 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); in vcn_v2_5_pause_dpg_mode()
Dvcn_v3_0.c1610 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); in vcn_v3_0_pause_dpg_mode()
1623 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, in vcn_v3_0_pause_dpg_mode()
1624 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); in vcn_v3_0_pause_dpg_mode()
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h109 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK macro
Dvcn_2_5_sh_mask.h1574 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK macro
Dvcn_2_0_0_sh_mask.h1571 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK macro
Dvcn_2_6_0_sh_mask.h3012 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK macro
Dvcn_3_0_0_sh_mask.h2120 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK macro
Dvcn_4_0_0_sh_mask.h6401 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK macro
Dvcn_4_0_3_sh_mask.h7217 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK macro