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Searched refs:TB_CFG_PORT (Results 1 – 13 of 13) sorted by relevance

/linux-6.6.21/drivers/thunderbolt/
Dusb4.c188 if (tb_port_read(port, &val, TB_CFG_PORT, in usb4_switch_check_wakes()
218 if (tb_port_read(port, &val, TB_CFG_PORT, in link_is_usb4()
396 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1); in usb4_switch_lane_bonding_possible()
431 ret = tb_port_read(port, &val, TB_CFG_PORT, in usb4_switch_set_wake()
454 ret = tb_port_write(port, &val, TB_CFG_PORT, in usb4_switch_set_wake()
1088 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1); in usb4_port_unlock()
1093 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1); in usb4_port_unlock()
1108 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1); in usb4_port_hotplug_enable()
1113 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1); in usb4_port_hotplug_enable()
1124 ret = tb_port_read(port, &val, TB_CFG_PORT, in usb4_port_set_configured()
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Dclx.c43 ret = tb_port_read(port, &phy, TB_CFG_PORT, in tb_port_pm_secondary_set()
53 return tb_port_write(port, &phy, TB_CFG_PORT, in tb_port_pm_secondary_set()
95 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_clx_supported()
118 ret = tb_port_read(port, &phy, TB_CFG_PORT, in tb_port_clx_set()
128 return tb_port_write(port, &phy, TB_CFG_PORT, in tb_port_clx_set()
150 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_clx()
Dtmu.c172 ret = tb_port_read(port, &data, TB_CFG_PORT, port->cap_tmu + offset, 1); in tb_port_tmu_write()
179 return tb_port_write(port, &data, TB_CFG_PORT, in tb_port_tmu_write()
210 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_tmu_is_unidirectional()
223 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_tmu_is_enhanced()
240 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_tmu_enhanced_enable()
250 return tb_port_write(port, &val, TB_CFG_PORT, in tb_port_tmu_enhanced_enable()
265 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_set_tmu_mode_params()
275 ret = tb_port_write(port, &val, TB_CFG_PORT, in tb_port_set_tmu_mode_params()
280 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_set_tmu_mode_params()
290 return tb_port_write(port, &val, TB_CFG_PORT, in tb_port_set_tmu_mode_params()
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Dcap.c58 tb_port_read(port, &dummy, TB_CFG_PORT, 0, 1); in tb_port_dummy_read()
80 ret = tb_port_read(port, &header, TB_CFG_PORT, offset, 1); in tb_port_next_cap()
99 ret = tb_port_read(port, &header, TB_CFG_PORT, offset, 1); in __tb_port_find_cap()
Dswitch.c476 res = tb_port_read(port, &phy, TB_CFG_PORT, port->cap_phy, 2); in tb_port_state()
593 TB_CFG_PORT, ADP_CS_4, 1); in tb_port_add_nfc_credits()
636 ret = tb_port_read(port, &phy, TB_CFG_PORT, in __tb_port_enable()
647 ret = tb_port_write(port, &phy, TB_CFG_PORT, in __tb_port_enable()
697 res = tb_port_read(port, &port->config, TB_CFG_PORT, 0, 8); in tb_init_port()
899 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_get_link_speed()
932 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_get_link_width()
951 ret = tb_port_read(port, &phy, TB_CFG_PORT, in tb_port_is_width_supported()
985 ret = tb_port_read(port, &val, TB_CFG_PORT, in tb_port_set_link_width()
1007 return tb_port_write(port, &val, TB_CFG_PORT, in tb_port_set_link_width()
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Dtunnel.c396 ret = tb_port_read(out, &val, TB_CFG_PORT, in tb_dp_cm_handshake()
403 ret = tb_port_write(out, &val, TB_CFG_PORT, in tb_dp_cm_handshake()
409 ret = tb_port_read(out, &val, TB_CFG_PORT, in tb_dp_cm_handshake()
599 ret = tb_port_read(in, &in_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
604 ret = tb_port_read(out, &out_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
610 ret = tb_port_write(out, &in_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
668 return tb_port_write(in, &out_dp_cap, TB_CFG_PORT, in tb_dp_xchg_caps()
696 ret = tb_port_read(in, &in_dp_cap, TB_CFG_PORT, in tb_dp_bandwidth_alloc_mode_enable()
701 ret = tb_port_read(out, &out_dp_cap, TB_CFG_PORT, in tb_dp_bandwidth_alloc_mode_enable()
864 ret = tb_port_read(in, &cap, TB_CFG_PORT, in tb_dp_bandwidth_mode_maximum_bandwidth()
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Ddma_port.c96 .space = TB_CFG_PORT, in dma_port_read()
137 .space = TB_CFG_PORT, in dma_port_write()
Ddebugfs.c153 ret = tb_port_write(port, &val, TB_CFG_PORT, offset, 1); in regs_write()
1103 ret = tb_port_read(port, &data, TB_CFG_PORT, cap + offset + i, 1); in cap_show_by_dw()
1127 ret = tb_port_read(port, data, TB_CFG_PORT, cap + offset, in cap_show()
1155 ret = tb_port_read(port, &header, TB_CFG_PORT, cap, 1); in port_cap_show()
1202 ret = tb_port_read(port, (u32 *)&header + 1, TB_CFG_PORT, in port_cap_show()
1246 ret = tb_port_read(port, data, TB_CFG_PORT, 0, ARRAY_SIZE(data)); in port_basic_regs_show()
Dicm.c1864 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1867 ret = pcie2cio_read(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, &val1); in icm_reset_phy_port()
1881 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
1886 ret = pcie2cio_write(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, val1); in icm_reset_phy_port()
1893 ret = pcie2cio_read(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, &val0); in icm_reset_phy_port()
1896 ret = pcie2cio_read(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, &val1); in icm_reset_phy_port()
1901 ret = pcie2cio_write(icm, TB_CFG_PORT, port0, PHY_PORT_CS1, val0); in icm_reset_phy_port()
1906 return pcie2cio_write(icm, TB_CFG_PORT, port1, PHY_PORT_CS1, val1); in icm_reset_phy_port()
Dtb_msgs.h17 TB_CFG_PORT = 1, enumerator
Deeprom.c381 res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1); in tb_drom_parse_entry_port()
Dctl.c1056 if (space == TB_CFG_PORT && in tb_cfg_get_error()
Dxdomain.c549 ret = tb_port_read(port, val, TB_CFG_PORT, in tb_xdp_link_state_status_response()
1297 ret = tb_port_read(port, &val, TB_CFG_PORT, port->cap_phy + LANE_ADP_CS_1, 1); in tb_xdomain_link_state_change()