Searched refs:SMU_INTERRUPT_CONTROL (Results 1 – 2 of 2) sorted by relevance
50 SR(SMU_INTERRUPT_CONTROL), \85 SR(SMU_INTERRUPT_CONTROL), \128 DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)165 DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)228 uint32_t SMU_INTERRUPT_CONTROL; member
668 REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); in dcn10_dmcu_setup_psr()