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Searched refs:SDMA1_PHASE0_QUANTUM__VALUE__SHIFT (Results 1 – 10 of 10) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/sdma1/
Dsdma1_4_0_sh_mask.h591 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
Dsdma1_4_2_2_sh_mask.h595 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT … macro
Dsdma1_4_2_sh_mask.h591 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_0_sh_mask.h1532 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
Doss_2_4_sh_mask.h1702 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
Doss_3_0_1_sh_mask.h2222 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
Doss_3_0_sh_mask.h2526 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/sdma/
Dsdma_4_4_0_sh_mask.h3100 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_sh_mask.h3077 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT … macro
Dgc_10_3_0_sh_mask.h3186 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT … macro