Searched refs:SCLK_PWM (Results 1 – 10 of 10) sorted by relevance
| /linux-6.6.21/include/dt-bindings/clock/ |
| D | exynos7-clk.h | 88 #define SCLK_PWM 11 macro
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| D | s5pv210.h | 191 #define SCLK_PWM 169 macro
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| D | rv1108-cru.h | 71 #define SCLK_PWM 121 macro
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| D | rk3328-cru.h | 49 #define SCLK_PWM 60 macro
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| /linux-6.6.21/arch/arm/boot/dts/rockchip/ |
| D | rv1108.dtsi | 200 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
212 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
224 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
236 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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| /linux-6.6.21/arch/arm64/boot/dts/rockchip/ |
| D | rk3328.dtsi | 456 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
467 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
478 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
490 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
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| /linux-6.6.21/drivers/clk/samsung/ |
| D | clk-s5pv210.c | 592 GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
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| D | clk-exynos7.c | 675 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
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| /linux-6.6.21/drivers/clk/rockchip/ |
| D | clk-rk3328.c | 465 COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0,
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| D | clk-rv1108.c | 627 COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0,
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