| /linux-6.6.21/include/dt-bindings/clock/ |
| D | rk3036-cru.h | 21 #define SCLK_EMMC 71 macro
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| D | rk3188-cru-common.h | 30 #define SCLK_EMMC 74 macro
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| D | rk3128-cru.h | 24 #define SCLK_EMMC 71 macro
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| D | rk3228-cru.h | 22 #define SCLK_EMMC 71 macro
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| D | rv1108-cru.h | 21 #define SCLK_EMMC 71 macro
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| D | rk3368-cru.h | 26 #define SCLK_EMMC 71 macro
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| D | px30-cru.h | 59 #define SCLK_EMMC 57 macro
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| D | rk3328-cru.h | 24 #define SCLK_EMMC 35 macro
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| D | rk3288-cru.h | 26 #define SCLK_EMMC 71 macro
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| D | rk3308-cru.h | 62 #define SCLK_EMMC 58 macro
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| D | rk3399-cru.h | 35 #define SCLK_EMMC 78 macro
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| /linux-6.6.21/Documentation/devicetree/bindings/mmc/ |
| D | arasan,sdhci.yaml | 212 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
215 assigned-clocks = <&cru SCLK_EMMC>;
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| /linux-6.6.21/drivers/clk/rockchip/ |
| D | clk-rk3036.c | 295 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
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| D | clk-rk3128.c | 321 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
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| D | clk-rk3228.c | 395 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
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| D | clk-rk3188.c | 404 COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0,
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| D | clk-rk3328.c | 631 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_2plls_24m_u480m_p, 0,
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| D | clk-rv1108.c | 728 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
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| D | clk-rk3368.c | 552 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
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| D | clk-rk3288.c | 535 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
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| D | clk-px30.c | 499 COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p,
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| D | clk-rk3308.c | 517 COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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| /linux-6.6.21/arch/arm/boot/dts/rockchip/ |
| D | rk3xxx.dtsi | 239 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
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| D | rk3036.dtsi | 282 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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| D | rk3128.dtsi | 163 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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