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Searched refs:RREG32_SOC15 (Results 1 – 25 of 112) sorted by relevance

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/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dnbio_v4_3.c42 u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); in nbio_v4_3_get_rev_id()
62 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); in nbio_v4_3_get_memsize()
70 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL); in nbio_v4_3_sdma_doorbell_range()
109 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL); in nbio_v4_3_vcn_doorbell_range()
111 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL); in nbio_v4_3_vcn_doorbell_range()
185 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL); in nbio_v4_3_ih_doorbell_range()
224 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); in nbio_v4_3_ih_control()
247 def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); in nbio_v4_3_update_medium_grain_clock_gating()
277 def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); in nbio_v4_3_update_medium_grain_light_sleep()
294 data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); in nbio_v4_3_get_clockgating_state()
[all …]
Dgfxhub_v2_1.c110 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); in gfxhub_v2_1_get_fb_location()
120 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; in gfxhub_v2_1_get_mc_fb_offset()
192 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_init_tlb_regs()
217 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_1_init_cache_regs()
230 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); in gfxhub_v2_1_init_cache_regs()
261 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); in gfxhub_v2_1_enable_system_domain()
394 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_gart_disable()
425 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v2_1_set_fault_enable_default()
507 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL); in gfxhub_v2_1_get_xgmi_info()
534 RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE), in gfxhub_v2_1_get_xgmi_info()
[all …]
Dnbio_v7_7.c43 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); in nbio_v7_7_get_rev_id()
62 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); in nbio_v7_7_get_memsize()
113 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN); in nbio_v7_7_enable_doorbell_aperture()
149 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, in nbio_v7_7_ih_doorbell_range()
177 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL); in nbio_v7_7_ih_control()
241 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3); in nbio_v7_7_init_registers()
260 def = data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL); in nbio_v7_7_update_medium_grain_clock_gating()
289 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2); in nbio_v7_7_update_medium_grain_light_sleep()
298 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1); in nbio_v7_7_update_medium_grain_light_sleep()
317 data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL); in nbio_v7_7_get_clockgating_state()
[all …]
Dsmuio_v13_0.c48 def = data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); in smuio_v13_0_update_rom_clock_gating()
69 data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); in smuio_v13_0_get_clock_gating_state()
85 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_die_id()
102 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_get_socket_id()
119 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_is_host_gpu_xgmi_supported()
Dgfx_v11_0.c764 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
777 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_regs()
1562 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1566 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1581 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1585 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1651 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); in gfx_v11_0_init_compute_vmid()
1694 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | in gfx_v11_0_get_tcc_info()
1695 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); in gfx_v11_0_get_tcc_info()
1716 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); in gfx_v11_0_constants_init()
[all …]
Dmmhub_v2_3.c179 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_3_init_system_aperture_regs()
190 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_init_tlb_regs()
209 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_3_init_cache_regs()
222 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_3_init_cache_regs()
253 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_3_enable_system_domain()
386 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_3_gart_disable()
393 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_3_gart_disable()
410 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v2_3_set_fault_enable_default()
497 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL); in mmhub_v2_3_update_medium_grain_clock_gating()
498 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); in mmhub_v2_3_update_medium_grain_clock_gating()
[all …]
Ddf_v1_7.c49 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); in df_v1_7_enable_broadcast_mode()
61 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
86 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
91 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_update_medium_grain_clock_gating()
107 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); in df_v1_7_get_clockgating_state()
Dsmu_v11_0_i2c.c51 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); in smu_v11_0_i2c_set_clock_gating()
87 u32 en_stat = RREG32_SOC15(SMUIO, in smu_v11_0_i2c_enable()
108 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR); in smu_v11_0_i2c_clear_status()
187 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_poll_tx_status()
195 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT); in smu_v11_0_i2c_poll_tx_status()
198 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); in smu_v11_0_i2c_poll_tx_status()
230 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); in smu_v11_0_i2c_poll_rx_status()
249 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_poll_rx_status()
298 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); in smu_v11_0_i2c_transmit()
422 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD); in smu_v11_0_i2c_receive()
[all …]
Dhdp_v5_0.c62 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_mem_power_gating()
63 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_update_mem_power_gating()
153 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_medium_grain_clock_gating()
189 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_get_clockgating_state()
199 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_get_clockgating_state()
212 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); in hdp_v5_0_init_registers()
Dgfxhub_v1_1.c53 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE); in gfxhub_v1_1_get_xgmi_info()
55 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE), in gfxhub_v1_1_get_xgmi_info()
60 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL); in gfxhub_v1_1_get_xgmi_info()
62 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE), in gfxhub_v1_1_get_xgmi_info()
Dmmhub_v2_0.c249 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v2_0_init_system_aperture_regs()
260 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_init_tlb_regs()
285 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_init_cache_regs()
298 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2); in mmhub_v2_0_init_cache_regs()
329 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL); in mmhub_v2_0_enable_system_domain()
454 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v2_0_gart_disable()
461 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL); in mmhub_v2_0_gart_disable()
483 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v2_0_set_fault_enable_default()
575 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid); in mmhub_v2_0_update_medium_grain_clock_gating()
578 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG); in mmhub_v2_0_update_medium_grain_clock_gating()
[all …]
Dmmhub_v3_0.c205 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_init_system_aperture_regs()
216 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_init_tlb_regs()
242 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_init_cache_regs()
255 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v3_0_init_cache_regs()
286 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v3_0_enable_system_domain()
411 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_gart_disable()
418 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_gart_disable()
440 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v3_0_set_fault_enable_default()
530 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v3_0_get_fb_location()
540 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; in mmhub_v3_0_get_mc_fb_offset()
[all …]
Dvcn_v1_0.c242 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { in vcn_v1_0_hw_fini()
456 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
467 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_disable_clock_gating()
472 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
482 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
505 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
529 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
556 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
582 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
591 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_enable_clock_gating()
[all …]
Djpeg_v3_0.c60 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING); in jpeg_v3_0_early_init()
177 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) in jpeg_v3_0_hw_fini()
229 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); in jpeg_v3_0_disable_clock_gating()
239 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v3_0_disable_clock_gating()
247 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); in jpeg_v3_0_disable_clock_gating()
259 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); in jpeg_v3_0_enable_clock_gating()
373 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v3_0_start()
418 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v3_0_dec_ring_get_rptr()
435 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v3_0_dec_ring_get_wptr()
462 ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & in jpeg_v3_0_is_idle()
Dmmhub_v1_0.c39 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); in mmhub_v1_0_get_fb_location()
40 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP); in mmhub_v1_0_get_fb_location()
131 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v1_0_init_system_aperture_regs()
142 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_init_tlb_regs()
165 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_init_cache_regs()
176 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); in mmhub_v1_0_init_cache_regs()
203 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); in mmhub_v1_0_enable_system_domain()
353 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); in mmhub_v1_0_gart_disable()
363 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_gart_disable()
383 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v1_0_set_fault_enable_default()
[all …]
Djpeg_v4_0.c203 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) in jpeg_v4_0_hw_fini()
258 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); in jpeg_v4_0_disable_clock_gating()
270 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); in jpeg_v4_0_disable_clock_gating()
282 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); in jpeg_v4_0_enable_clock_gating()
294 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); in jpeg_v4_0_enable_clock_gating()
406 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); in jpeg_v4_0_start()
435 header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE); in jpeg_v4_0_start_sriov()
480 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); in jpeg_v4_0_start_sriov()
504 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); in jpeg_v4_0_start_sriov()
565 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); in jpeg_v4_0_dec_ring_get_rptr()
[all …]
Dnbio_v7_4.c115 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE); in nbio_v7_4_get_rev_id()
117 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); in nbio_v7_4_get_rev_id()
136 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); in nbio_v7_4_get_memsize()
237 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); in nbio_v7_4_ih_doorbell_range()
297 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); in nbio_v7_4_ih_control()
352 baco_cntl = RREG32_SOC15(NBIO, 0, mmBACO_CNTL); in nbio_v7_4_init_registers()
372 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
374 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); in nbio_v7_4_handle_ras_controller_intr_no_bifring()
428 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE); in nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring()
430 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); in nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring()
[all …]
Dnbio_v2_3.c87 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); in nbio_v2_3_get_rev_id()
106 return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); in nbio_v2_3_get_memsize()
190 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); in nbio_v2_3_ih_doorbell_range()
214 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); in nbio_v2_3_ih_control()
391 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2); in nbio_v2_3_program_ltr()
435 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); in nbio_v2_3_program_aspm()
441 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5); in nbio_v2_3_program_aspm()
471 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); in nbio_v2_3_program_aspm()
477 def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5); in nbio_v2_3_program_aspm()
543 reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL); in nbio_v2_3_clear_doorbell_interrupt()
[all …]
Dmmhub_v3_0_1.c204 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); in mmhub_v3_0_1_init_system_aperture_regs()
215 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_init_tlb_regs()
235 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_1_init_cache_regs()
248 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); in mmhub_v3_0_1_init_cache_regs()
279 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); in mmhub_v3_0_1_enable_system_domain()
398 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); in mmhub_v3_0_1_gart_disable()
405 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); in mmhub_v3_0_1_gart_disable()
422 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v3_0_1_set_fault_enable_default()
506 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); in mmhub_v3_0_1_get_fb_location()
515 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; in mmhub_v3_0_1_get_mc_fb_offset()
[all …]
Dhdp_v5_2.c54 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_mem_power_gating()
55 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_update_mem_power_gating()
136 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_medium_grain_clock_gating()
165 tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_get_clockgating_state()
175 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_get_clockgating_state()
Dsmuio_v13_0_3.c42 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_3_get_die_id()
59 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_3_get_socket_id()
78 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); in smuio_v13_0_3_get_pkg_type()
Dvcn_v4_0.c314 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v4_0_hw_fini()
588 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v4_0_disable_static_power_gating()
613 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); in vcn_v4_0_enable_static_power_gating()
670 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
676 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); in vcn_v4_0_disable_clock_gating()
701 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
724 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); in vcn_v4_0_disable_clock_gating()
751 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); in vcn_v4_0_disable_clock_gating()
838 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_enable_clock_gating()
844 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); in vcn_v4_0_enable_clock_gating()
[all …]
/linux-6.6.21/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega10_thermal.c74 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_get_fan_speed_pwm()
76 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), in vega10_fan_ctrl_get_fan_speed_pwm()
104 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
132 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
135 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
141 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
144 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
161 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
165 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_default_mode()
263 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_set_fan_speed_pwm()
[all …]
Dvega20_thermal.c95 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega20_fan_ctrl_set_static_mode()
98 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega20_fan_ctrl_set_static_mode()
124 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_get_fan_speed_pwm()
126 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), in vega20_fan_ctrl_get_fan_speed_pwm()
152 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega20_fan_ctrl_set_fan_speed_pwm()
163 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), in vega20_fan_ctrl_set_fan_speed_pwm()
206 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), in vega20_fan_ctrl_set_fan_speed_rpm()
223 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); in vega20_thermal_get_temperature()
260 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); in vega20_thermal_set_temperature_range()
/linux-6.6.21/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dsmu9_smumgr.c74 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103); in smu9_wait_for_response()
83 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
171 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102); in smu9_get_argument()
173 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); in smu9_get_argument()

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